📄 def21160.h
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#define CP8 0x93 /* Points to next DMA8 parameters */
#define GP8 0x94 /* DMA8 General purpose / 2-D DMA */
#define DB8 0x95 /* DMA8 General purpose / 2-D DMA */
#define DA8 0x96 /* DMA8 General purpose / 2-D DMA */
#define II9 0x98 /* Internal DMA9 memory address */
#define IM9 0x99 /* Internal DMA9 memory access modifier */
#define C9 0x9a /* Contains number of DMA9 transfers remainnig */
#define CP9 0x9b /* Points to next DMA9 parameters */
#define GP9 0x9c /* DMA9 General purpose / 2-D DMA */
#define DB9 0x9d /* DMA9 General purpose / 2-D DMA */
#define DA9 0x9e /* DMA9 General purpose / 2-D DMA */
/* Emulation/Breakpoint Registers (remapped from UREG space) */
/* NOTES:
- These registers are ONLY accessible by the core
- It is *highly* recommended that these facilities be accessed only
through the ADI emulator routines
*/
/* Core Emulation HWBD Registers */
#define PSA1S 0xa0 /* Instruction address start #1 */
#define PSA1E 0xa1 /* Instruction address end #1 */
#define PSA2S 0xa2 /* Instruction address start #2 */
#define PSA2E 0xa3 /* Instruction address end #2 */
#define PSA3S 0xa4 /* Instruction address start #3 */
#define PSA3E 0xa5 /* Instruction address end #3 */
#define PSA4S 0xa6 /* Instruction address start #4 */
#define PSA4E 0xa7 /* Instruction address end #4 */
#define PMDAS 0xa8 /* Program Data address start */
#define PMDAE 0xa9 /* Program Data address end */
#define DMA1S 0xaa /* Data address start #1 */
#define DMA1E 0xab /* Data address end #1 */
#define DMA2S 0xac /* Data address start #2 */
#define DMA2E 0xad /* Data address end #2 */
#define EMUN 0xae /* hwbp hit-count register */
/* IOP Emulation HWBP Bounds Registers */
#define IOAS 0xb0 /* IOA Upper Bounds Register */
#define IOAE 0xb1 /* IOA Lower Bounds Register */
#define EPAS 0xb2 /* EPA Upper Bounds Register */
#define EPAE 0xb3 /* EPA Lower Bounds Register */
#define LBUF0 0xc0 /* Link buffer 0 */
#define LBUF1 0xc2 /* Link buffer 1 */
#define LBUF2 0xc4 /* Link buffer 2 */
#define LBUF3 0xc6 /* Link buffer 3 */
#define LBUF4 0xc8 /* Link buffer 4 */
#define LBUF5 0xca /* Link buffer 5 */
#define LCTL0 0xcc /* Link buffer control */
#define LCTL1 0xcd /* Link buffer control */
#define LCOM 0xce /* Link common control */
#define LAR 0xcf /* Link assignment register */
#define LSRQ 0xd0 /* Link service request and mask register */
#define LPATH1 0xd1 /* Link path register 1 */
#define LPATH2 0xd2 /* Link path register 2 */
#define LPATH3 0xd3 /* Link path register 3 */
#define LPCNT 0xd4 /* Link path counter */
#define CNST1 0xd5 /* Link port constant 1 register */
#define CNST2 0xd6 /* Link port constant 2 register */
#define STCTL0 0xe0 /* Serial Port 0 Transmit Control Register */
#define SRCTL0 0xe1 /* Serial Port 0 Receive Control Register */
#define TX0 0xe2 /* Serial Port 0 Transmit Data Buffer */
#define RX0 0xe3 /* Serial Port 0 Receive Data Buffer */
#define TDIV0 0xe4 /* Serial Port 0 Transmit Divisor */
#define TCNT0 0xe5 /* Serial Port 0 Transmit Count Reg */
#define RDIV0 0xe6 /* Serial Port 0 Receive Divisor */
#define RCNT0 0xe7 /* Serial Port 0 Receive Count Reg */
#define MTCS0 0xe8 /* Serial Port 0 Mulitchannel Transmit Selector */
#define MRCS0 0xe9 /* Serial Port 0 Mulitchannel Receive Selector */
#define MTCCS0 0xea /* Serial Port 0 Mulitchannel Transmit Selector */
#define MRCCS0 0xeb /* Serial Port 0 Mulitchannel Receive Selector */
#define KEYWD0 0xec /* Serial Port 0 Receive Comparison Register */
#define KEYMASK0 0xed /* Serial Port 0 Receive Comparison Mask Register */
#define SPATH0 0xee /* Serial Port 0 Path Length (Mesh Multiprocessing) */
#define SPCNT0 0xef /* Serial Port 0 Path Counter (Mesh Multiprocessing) */
#define STCTL1 0xf0 /* Serial Port 1 Transmit Control Register */
#define SRCTL1 0xf1 /* Serial Port 1 Receive Control Register */
#define TX1 0xf2 /* Serial Port 1 Transmit Data Buffer */
#define RX1 0xf3 /* Serial Port 1 Receive Data Buffer */
#define TDIV1 0xf4 /* Serial Port 1 Transmit Divisor */
#define TCNT1 0xf5 /* Serial Port 1 Transmit Count Reg */
#define RDIV1 0xf6 /* Serial Port 1 Receive Divisor */
#define RCNT1 0xf7 /* Serial Port 1 Receive Count Reg */
#define MTCS1 0xf8 /* Serial Port 1 Mulitchannel Transmit Selector */
#define MRCS1 0xf9 /* Serial Port 1 Mulitchannel Receive Selector */
#define MTCCS1 0xfa /* Serial Port 1 Mulitchannel Transmit Selector */
#define MRCCS1 0xfb /* Serial Port 1 Mulitchannel Receive Selector */
#define KEYWD1 0xfc /* Serial Port 1 Receive Comparison Register */
#define KEYMASK1 0xfd /* Serial Port 1 Receive Comparison Mask Register */
#define SPATH1 0xfe /* Serial Port 1 Path Length (Mesh Multiprocessing) */
#define SPCNT1 0xff /* Serial Port 1 Path Counter (Mesh Multiprocessing) */
/*------------------------------------------------------------------------------*/
/* IOP Register Bit Definitions */
/*------------------------------------------------------------------------------*/
/* SYSCON Register */
#define SRST 0x00000001 /* Soft Reset */
#define BSO 0x00000002 /* Boot Select Override */
#define IIVT 0x00000004 /* Internal Interrupt Vector Table */
#define IWT 0x00000008 /* Instruction word transfer (0 = data, 1 = inst) */
#define HPM000 0x00000000 /* Host packing mode: None */
#define HPM001 0x00000010 /* Host packing mode: 16/48 */
#define HPM010 0x00000020 /* Host packing mode: 16/64 */
#define HPM011 0x00000030 /* Host packing mode: 32/48 */
#define HPM100 0x00000040 /* Host packing mode: 32/64 */
#define HMSWF 0x00000080 /* Host packing order (0 = LSW first, 1 = MSW) */
#define HPFLSH 0x00000100 /* Host pack flush */
#define IMDW0 0x00000200 /* Internal memory block 0, extended data (40 bit) */
#define IMDW1 0x00000400 /* Internal memory block 1, extended data (40 bit) */
#define ADREDY 0x00000800 /* Active Drive Ready */
#define BHD 0x00010000 /* Buffer Hand Disable */
#define EBPR00 0x00000000 /* External bus priority: Even */
#define EBPR01 0x00020000 /* External bus priority: Core has priority */
#define EBPR10 0x00040000 /* External bus priority: IO has priority */
#define DCPR 0x00080000 /* Select rotating access priority on DMA10 - DMA13 */
#define LDCPR 0x00100000 /* Select rotating access priority on DMA4 - DMA9 */
#define PRROT 0x00200000 /* Select rotating prio between LPort and EPort */
#define COD 0x00400000 /* Clock Out Disable */
#define IMGR 0x10000000 /* Internal memory block grouping (for the MSP) */
/* SYSTAT Register */
#define HSTM 0x00000001 /* Host is the Bus Master */
#define BSYN 0x00000002 /* Bus arbitration logic is synchronized */
#define CRBM 0x00000070 /* Current ADSP21160 Bus Master */
#define IDC 0x00000700 /* ADSP21160 ID Code */
#define DWPD 0x00001000 /* Direct write pending (0 = none, 1 = pending) */
#define VIPD 0x00002000 /* Vector interrupt pending (1 = pending) */
#define HPS 0x0000c000 /* Host pack status */
#define CRAT 0x00070000 /* CLK_CFG(3-0), Core:CLKIN clock ratio */
/* WAIT Register */
#define EB0S1 0x00000001 /* External Bank 0 Sync, min 2-cycle reads, 1-cycle writes */
#define EB0S2 0x00000002 /* External Bank 0 Sync, min 2-cycle reads, 2-cycle writes */
#define EB1S1 0x00000020 /* External Bank 1 Sync, min 2-cycle reads, 1-cycle writes */
#define EB1S2 0x00000040 /* External Bank 1 Sync, min 2-cycle reads, 2-cycle writes */
#define EB2S1 0x00000400 /* External Bank 2 Sync, min 2-cycle reads, 1-cycle writes */
#define EB2S2 0x00000800 /* External Bank 2 Sync, min 2-cycle reads, 2-cycle writes */
#define EB3S1 0x00008000 /* External Bank 3 Sync, min 2-cycle reads, 1-cycle writes */
#define EB3S2 0x00010000 /* External Bank 3 Sync, min 2-cycle reads, 2-cycle writes */
#define UBS1 0x00100000 /* Unbanked Sync, min 2-cycle reads, 1-cycle writes */
#define UBS2 0x00200000 /* Unbanked Sync, min 2-cycle reads, 2-cycle writes */
#define HIDMA 0x80000000 /* Single idle cycle for DMA handshake */
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