board.c

摩托罗拉冷火系列bootloader源码

// ======================================================================
// Board.c - (Implementation File)
//
// Filename: Board.c
// Date:     September 20, 2002
// By:       Greg Robertson, P.Eng.
//
// Author:	 Original work and assistance by Ken Treis.
//			 Additional individuals shown below.
//
// Description:
// 
//			This file contains all the initial configurations for the
//			COLILO bootloader to initialize the LDC controller.
//
//			This code is taken directly from the code for the M5272C3
//			evaluation board from Motorola.  Only specific sections have
//			been altered for the LDC.
//
//			Specifics for Hamilton Digital Designs LTD.
//
// History:
//
//
// ======================================================================

// ======================================================================
// Pre-Defines
// ----------------------------------------------------------------------
#define MCF_CLK 33000000		// Prototype's 33 MHz - Overrides default 66 MHz

// ======================================================================
// Includes
// ----------------------------------------------------------------------
#include "arch.h"
#include "mcfuart.h"

// ======================================================================
// Constants and Structures
// ----------------------------------------------------------------------
char	ident[] = "HDD 5272 LDC";
char	copyright[] = "(C) 1999, Moreton Bay Ventures, Rob Scott, Roland Seuhs\n(C) 2001 Key Technology, Travis Griggs, Ken Treis";

// ======================================================================
// External variables
// ----------------------------------------------------------------------
extern unsigned int downloadPort;
extern unsigned int image_size;
extern unsigned char *xfer_addr;
extern unsigned char *down_addr;
extern unsigned char *dest_addr;
extern unsigned char *source_addr;

extern unsigned long consoleBase;

// ======================================================================
// Functions
// ======================================================================

// ----------------------------------------------------------------------
// Setting up MAIN serial port (as a console port).
void configureConsole()
{
	consoleBase = MCFUART_BASE2;
	configureSerial(consoleBase, 19200, MCF_CLK);
}

// ----------------------------------------------------------------------
// Setting up Auxilary Serial Port.
void configureAuxSerial()
{
	configureSerial(MCFUART_BASE1, 115200, MCF_CLK);
}

// ----------------------------------------------------------------------
void setLED() {};

// ----------------------------------------------------------------------
// Setting up Image Parameters
void setImageParams()
{
	// ------------------------------------------------------------------
	downloadPort = 0;
	image_size   = 0x000e0000;

	// ------------------------------------------------------------------
	// Specify:  
	//	Source Address:  Begin of Image source in flash (where decompression starts)
	//	Down Address:	 Download of image via ZMODEM (start location to place image)
	// 
	//  Modifications made for LDC.
	//
	source_addr = (unsigned char *)0xf0020000;
	down_addr   = (unsigned char *)0xf0020000;

	// ------------------------------------------------------------------
	// Specify:  
	//	Transfer Address:	 RAM Address (legacy)
	//	Destination Address: RAM Address (legacy)
	//
	xfer_addr   = (unsigned char *)0x00020000;
	dest_addr   = (unsigned char *)0x00020000;
}

// ----------------------------------------------------------------------
// CORE Setting up of LDC Controller.
void setupBoard()
{
	// ------------------------------------------------------------------
	volatile unsigned char	*mbar;
	mbar = (volatile unsigned char *) MCF_MBAR;

	// ------------------------------------------------------------------
	// stuff that was added for dbug compliance (sim_init)
	mbar_writeShort(MCFSIM_SCR, 0x0003);
	mbar_writeShort(MCFSIM_SPR, 0xFFFF);
	mbar_writeLong(MCFSIM_ICR1, 0x88888888);
	mbar_writeLong(MCFSIM_ICR2, 0x88888888);
	mbar_writeLong(MCFSIM_ICR3, 0x88888888);
	mbar_writeLong(MCFSIM_ICR4, 0x88880000);
	mbar_writeLong(MCFSIM_PITR, 0x00000000);
	mbar_writeByte(MCFSIM_PIVR, 0x00000040);

	// ------------------------------------------------------------------
	// Setting up serial console
	mbar_writeShort(MCFSIM_PADDR, 0x0000);		// Reset
	mbar_writeShort(MCFSIM_PBDDR, 0x0000);		// Reset
	mbar_writeLong(MCFSIM_PACNT, 0x00000000);	// Reset
	mbar_writeLong(MCFSIM_PBCNT, 0x55554155);	// PBCNT allows the console to work
	mbar_writeLong(MCFSIM_PDCNT, 0x000002aa);	// PDCNT set for UART_1 to be serial (needed for CONSOLE)

	// ------------------------------------------------------------------
	// ------------------------------------------------------------------
	// NOTES: Initialization of chip-selects to setup memory devices
	//
	// Each Chip Select is composed of a CSBR and a CSOR (Base and Option 
	// Register).  Both need to be set.
	//
	// CSBR -- chip select base register
	//
	//	  0000 0000 0000 0000 0000 0000 0000 0000
	//	  ++++ ++++ ++++ ++++ ++++ ---------------- BA       : Base Address
	//	                         . ++ ------------- EDI      : External Bus Interface
	//	                         . ..++ ----------- BW       : Bus Width 
	//	                         . .... + --------- SUPER    : Supervisor mode
	//	                         . .... .++ ------- TT       : Transfer Type
	//	                         . .... ...+ ++ --- TM       : Transfer Modifier
	//	                         . .... .... ..+ -- CTM      : Compare TM
	//	                         . .... .... ...+ - ENABLE   : Enable
	//
	// CSOR -- chip select option register
	//
	//	  0000 0000 0000 0000 0000 0000 x000 0000
	//	  ++++ ++++ ++++ ++++ ++++ ---------------- BAM      : Base Address Mask
	//	                         . + -------------- ASET     : Address setup enable
	//	                         . .+ ------------- WRAH     : Enable/disable addr hold
	//	                         . ..+ ------------ RDAH     : Enable/disable addr & attribute
	//	                         . ...+ ----------- EXTBURST : Enable Extended Burst
	//	                         . .... + --------- RESERVED
	//	                         . .... .+++ ++ --- WS       : Wait state generator
	//	                         . .... .... ..+ -- RW       : Read Only Mode
	//	                         . .... .... ...+ - MRW      : enable/disable RW
	//
	// ------------------------------------------------------------------
	// ------------------------------------------------------------------
	
	// ------------------------------------------------------------------
	// CS0: FLASH
	//
	//	For CSBR0:
	//	  1111 0000 0000 0000 0000 ---------------- BA       : 0xF0000000
	//	                         . 00 ------------- EDI      : 32 Bits
	//	                         . ..00 ----------- BW       : 32 Bit Bus Width
	//	                         . .... 0 --------- SUPER    : NO Supervisor mode
	//	                         . .... .00 ------- TT       : NO Transfer Type
	//	                         . .... ...0 00 --- TM       : NO Transfer Modifier
	//	                         . .... .... ..0 -- CTM      : NO Compare TM
	//	                         . .... .... ...1 - ENABLE   : Enable
	//
	//    1111 0000 0000 0000 0000 0010 0000 0001 -> 0xF0000001
	//
	//	For CSOR0:
	//	  1111 1111 1000 0000 0000 ---------------- BAM      : Base Address Mask (look below)
	//	                         . 0 -------------- ASET     : Assert rising clock edge
	//	                         . .0 ------------- WRAH     : Do Not Hold
	//	                         . ..0 ------------ RDAH     : Do Not Hold
	//	                         . ...0 ----------- EXTBURST : Not Enable
	//	                         . .... 0 --------- RESERVED : ZEROED
	//	                         . .... .101 00 --- WS       : 20 Wait States
	//	                         . .... .... ..0 -- RW       : Doe not matter.
	//	                         . .... .... ...0 - MRW      : Is Read and Write
	//
	//		Base Address Mask: 2^23 = 8MBytes 
	//						   (i.e. the binary zeros in FF800000 is 23)
	//
	//    1111 1111 1000 0000 0000 0000 0001 0100 -> 0xFF800050
	//
	// Modifcations for HDD-LDC board
	mbar_writeLong(MCFSIM_CSBR0, 0xF0000001);
	mbar_writeLong(MCFSIM_CSOR0, 0xFF800050);

	// ------------------------------------------------------------------
	// CS2: External 512K SRAM -- may or may not be there
	//mbar_writeLong(MCFSIM_CSBR2, 0x30000001);
	//mbar_writeLong(MCFSIM_CSOR2, 0xFFF80000);

	// ------------------------------------------------------------------
	// CS7: SDRAM
	// 
	//	For CSBR7:
	//	  0000 0000 0000 0000 0000 ---------------- BA       : 0x00000000
	//	                         . 01 ------------- EDI      : For SDRAM
	//	                         . ..00 ----------- BW       : 32 Bits Bus Width 
	//	                         . .... 0 --------- SUPER    : NO Supervisor mode
	//	                         . .... .00 ------- TT       : NO Transfer Type
	//	                         . .... ...0 00 --- TM       : NO Transfer Modifier
	//	                         . .... .... ..0 -- CTM      : NO Compare TM
	//	                         . .... .... ...1 - ENABLE   : Enable
	//
	//    0000 0000 0000 0000 0000 0100 0000 0001 -> 0x00000401
	//
	//	For CSOR7:
	//	  1111 1110 0000 0000 0000 ---------------- BAM      : Base Address Mask (look below)
	//	                         . 0 -------------- ASET     : Assert rising clock edge
	//	                         . .0 ------------- WRAH     : Do Not Hold
	//	                         . ..0 ------------ RDAH     : Do Not Hold
	//	                         . ...1 ----------- EXTBURST : Not Enable
	//	                         . .... 0 --------- RESERVED : ZEROED
	//	                         . .... .111 11 --- WS       : Must be set to 0x1F
	//	                         . .... .... ..0 -- RW       : Does not matter.
	//	                         . .... .... ...0 - MRW      : Is Read and Write
	//
	//		Base Address Mask: 2^25 = 32 MBytes (MAXIMUM value for LDC)
	//						   (i.e. the binary zeros in FE000000 is 25)
	//
	//    1111 1110 0000 0000 0000 0000 0111 1100 -> 0xFE00007C
	//
	// Modifcations for HDD-LDC board
	mbar_writeLong(MCFSIM_CSBR7, 0x00000401);
	mbar_writeLong(MCFSIM_CSOR7, 0xFE00017C);
	
	// ------------------------------------------------------------------
	// CS1 CS3, CS4, CS5, and CS6 are unused on the M5272C3.
	mbar_writeLong(MCFSIM_CSBR1, 0);
	mbar_writeLong(MCFSIM_CSOR1, 0);
	mbar_writeLong(MCFSIM_CSBR2, 0);
	mbar_writeLong(MCFSIM_CSOR2, 0);
	mbar_writeLong(MCFSIM_CSBR3, 0);
	mbar_writeLong(MCFSIM_CSOR3, 0);
	mbar_writeLong(MCFSIM_CSBR4, 0);
	mbar_writeLong(MCFSIM_CSOR4, 0);
	mbar_writeLong(MCFSIM_CSBR5, 0);
	mbar_writeLong(MCFSIM_CSOR5, 0);
	mbar_writeLong(MCFSIM_CSBR6, 0);
	mbar_writeLong(MCFSIM_CSOR6, 0);
}

// ----------------------------------------------------------------------
// Initialize SDRAM with a dummy write.
void setupDRAM()
{
	volatile unsigned char *mbar = (unsigned char *)MCF_MBAR;

	// Initialize SDRAM for the LDC
	mbar_writeLong(MCFSIM_SDTR, 0x3515);
	mbar_writeLong(MCFSIM_SDCR, 0x6511);

	// Dummy write to start SDRAM
	*((volatile unsigned long *)0) = 0;
}