📄 os_cpu_a.asm
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*****************************************************************************
*
* component :
* TMS320C6x Real Time Operating System
*
* module name : ucos6201.ASM
*
* subcomponent:
*
******************************************************************************
*
* function :
* Contains code for the scheduling.
* The code has to be in assembler as it is interfaced with the
* UC/OS code.
* description :
*
******************************************************************************
*
*
* dependencies:
* TMS320C6201 DSP
* TI compiler version 3 with the following switches
* TMS320C6x C Compiler Shell Version 3.00
*
* cl6x -b -pdv -g -k -ss -s -q -mw -mi50 -o3 -on2 -os -x2 -al
* -frc_obj -fsc_asm asmfiles/*.asm software\ucos-II\tms6201\OS_CPU_a.asm
* *.c -z link.cmd -l rts6201.lib -o product/kern2.out
*
* One context switch (130 MHz) takes 550 nano sec.
* One context switch (130 MHz) by interrupt takes 1 microsec
* Thus the normal 8000 context switches per second is
* at maximum 8 millisec, 0.8 % cpu load.
* Not bad at all!!!
*
* author : Kenneth Blake -
* history :
*
*
******************************************************************************/
*****************************************************************
*
* ucos6201.ASM
* Real Time Operating System
*****************************************************************
FP .set A15
DP .set B14
SP .set B15
_StartAddress .set 0+4
_A0 .set 4 +4
_A1 .set 8 +4
_A2 .set 12 +4
_A3 .set 16 +4
_A4 .set 20 +4
_A5 .set 24 +4
_A6 .set 28 +4
_A7 .set 32 +4
_A8 .set 36 +4
_A9 .set 40 +4
_A10 .set 44 +4
_A11 .set 48 +4
_A12 .set 52 +4
_A13 .set 56 +4
_A14 .set 60 +4
_A15 .set 64 +4
_B0 .set 68 +4
_B1 .set 72 +4
_B2 .set 76 +4
_B3 .set 80 +4
_B4 .set 84 +4
_B5 .set 88 +4
_B6 .set 92 +4
_B7 .set 96 +4
_B8 .set 100 +4
_B9 .set 104 +4
_B10 .set 108 +4
_B11 .set 112 +4
_B12 .set 116 +4
_B13 .set 120 +4
_B14 .set 124 +4
_B15 .set 128 +4
_AMR .set 132 +4
_CSR .set 136 +4
_IER .set 140 +4
_IRP .set 144 +4
_Framesize .set 148 +4
DelaySlot_for_Branch .set 5
.global $bss
.global __vector ; /* Memory location for default */
.global _TimerZeroTick
.global _Always_Enabled_Interrupts
.global _OSStartHighRdy
.global _OSTCBHighRdy
.global _OSTCBCur
.global _OSPrioCur
.global _OSPrioHighRdy
.global _OSCtxSw
.global _OSIntCtxSw
.global _c6201_Restor
.global _c6201_Save
.global _C6201_Register_Initialisation
.global _OSTaskSwHook
.global _ReturnCurrentDP
.global _OSRunning
.align 32
.global _ReturnCurrentDP
;----------------------------------------------------------------------
; 140 | int ReturnCurrentDP( void )
;----------------------------------------------------------------------
;******************************************************************************
;* FUNCTION NAME: _ReturnCurrentDP *
;* *
;* Regs Modified : A4 *
;* Regs Used : A4,B3 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
_ReturnCurrentDP:
;** --------------------------------------------------------------------------*
;----------------------------------------------------------------------
;----------------------------------------------------------------------
mv DP,a4
;** --------------------------------------------------------------------------*
B .S2 B3 ; |144|
NOP 5
; BRANCH OCCURS ; |144|
;----------------------------------------------;
; Initialise the processors registers with ;
; defined values ;
;----------------------------------------------;
.align 32
_C6201_Register_Initialisation
MVK .S2 0x0,B0
b
mvc B0,AMR
mvc B0,ISR
mvc B0,ICR
mvc B0,IER
mvc B0,IRP
mvc B0,ICR
mvc B0,NRP
; MVK .S2 0x100,B0 big endian
mvc B0,CSR
mvkl .s2 __vector,B0
mvkh .s2 __vector,B0
mvc B0,ISTP
MVK .S1 0x0A0,A0
MVK .S1 0x0A1,A1
MVK .S1 0x0A2,A2
MVK .S1 0x0A3,A3
MVK .S1 0x0A4,A4
MVK .S1 0x0A5,A5
MVK .S1 0x0A6,A6
MVK .S1 0x0A7,A7
MVK .S1 0x0A8,A8
MVK .S1 0x0A9,A9
MVK .S1 0x0A10,A10
MVK .S1 0x0A11,A11
MVK .S1 0x0A12,A12
MVK .S1 0x0A13,A13
MVK .S1 0x0A14,A14
; MVK .S1 0x0,A15 ; Frame pointer
MVK .S2 0x0B0,B0
MVK .S2 0x0B1,B1
MVK .S2 0x0B2,B2
; MVK .S2 0x0B3,B3 Return address
MVK .S2 0x0B4,B4
MVK .S2 0x0B5,B5
MVK .S2 0x0B6,B6
MVK .S2 0x0B7,B7
MVK .S2 0x0B8,B8
MVK .S2 0x0B9,B9
MVK .S2 0x0B10,B10
MVK .S2 0x0B11,B11
MVK .S2 0x0B12,B12
MVK .S2 0x0B13,B13
; MVK .S2 0xA140,B14 ; data pointer
; MVK .S2 0x0,B15 ; Stack pointer
B .S2 B3 ; |133|
NOP 5
.align 32
_c6201_Save
*
* Save registers in INITIAL_REGISTER_FRAME format
* Also save the stack pointer in the TCB
* for potential interrupt context switch
* IRP contains the return address for the interrupt handler
* B3 the return address in the interrupt handler
* On the stack is the saved B3
* RUNS IN D I S A B L E D M O D E
; SP--> Free 0
; xxxxx 4
; User B3 8
; B3 contains return address in interrupt handler
; IRP contains the address of the interrupted environment
; The environments B# value is on the stack
; SP--> User B3
;
addk .s2 (12 -_Framesize),SP ; Push one Frame
; SP--> Free
; Frame start
; .....
; ......
; .....
; .....
; Frame IRP Including User B3
;
;
; DISABLED INTERRUPT MODE
;--------------------------------------------------------------;
; Save the Return address pointing within the interrupt handler
; It is in register B3, written by the caller
;--------------------------------------------------------------;
;---------------------------;
; Save the registers ;
;---------------------------;
STW .D2T2 B0,*+SP(_B0) ; ; Save B0
|| mvc AMR,B0 ; B0 = AMR
STW .D2T2 B1,*+SP(_B1) ; ; Save B1
|| mvc CSR,B1 ; B1 = CSR
STW .D2T2 B2,*+SP(_B2) ; ; Save B2
|| mvc IER,B2 ; B2 =Interrupt enable register
LDW .D2T2 *+DP(_Always_Enabled_Interrupts),B0 ; |92|
STW .D2T2 B0,*+SP(_AMR) ; ; Save AMR
STW .D2T2 B1,*+SP(_CSR) ; ; Save CSR
STW .D2T2 B2,*+SP(_IER) ; ; Save IER
;---------------------------------------------;
; Set the Global Interrupt Enable GIE and ;
; Previous Global Interrupt Enable PGIE ;
; in CSR ;
;---------------------------------------------;
STW .D2T2 B4,*+SP(_B4) ; ; Save B4
|| mvc IRP,B4 ; The return address in the interrupted environment
STW .D2T2 B4,*+SP (_StartAddress) ; Save return address in interrupt handler start address
|| or 3,B1,B1 ; Set GIE
|| MVC .S2 B0,IER ; IER = Always_Enabled_Interrupts
STW .D2T2 B5,*+SP(_B5) ;
|| mvc b1,CSR ;Enable Always_Enabled_Interrupts
;---------------------------------------------------;
; From here on the always enabled interrupts may ;
; interrupt the processing ;
;---------------------------------------------------;
STW .D2T2 B6,*+SP(_B6) ;
STW .D2T2 B7 ,*+SP(_B7 ) ;
STW .D2T2 B8 ,*+SP(_B8 ) ;
STW .D2T2 B9 ,*+SP(_B9 ) ;
STW .D2T2 B10,*+SP(_B10) ;
STW .D2T2 B11,*+SP(_B11) ;
STW .D2T2 B12,*+SP(_B12) ;
STW .D2T2 B13,*+SP(_B13) ;
STW .D2T2 B14,*+SP(_B14) ;
STW .D2T1 A0,*+SP(_A0) ; Save A0
;----------------------------------------------------------;
; Save the interrupted environments B3 Register contents
; It is currently at the IRP position in the frame
; Get it into A0
;----------------------------------------------------------;
LDW *+SP (_IRP),A0 ; A0 = The interrupted environments B3
STW .D2T1 A1,*+SP(_A1) ; Save A1
STW .D2T1 A2,*+SP(_A2) ; Save A2
STW .D2T1 A3,*+SP(_A3) ; Save A3
STW .D2T1 A4,*+SP(_A4) ; Save A4
;------------------------------------------------------;
; Save the Environments B3 contents which is in A0 ;
;------------------------------------------------------;
STW A0,*+SP(_B3) ; Save B3 <------- B3 B3 B3
STW .D2T1 A5,*+SP(_A5) ;
STW .D2T1 A6,*+SP(_A6) ;
STW .D2T1 A7,*+SP(_A7) ;
STW .D2T1 A8,*+SP(_A8) ;
STW .D2T1 A9,*+SP(_A9) ;
|| MV .L1X SP,A0 ; A0 = SP
STW .D2T1 A10,*+SP(_A10) ;
;------------------------------------------------------------;
; Calculate a correct SP value for ;
; the entry in the TCB. ;
; Put it in the TCB at the B15 position (that is the SP) ;
;------------------------------------------------------------;
|| addk .s1 (_IRP),A0 ; A0 = SP + FRAME Correct SP for POP of TCB
STW .D2T1 A0,*+SP(_B15) ; B15 = A0 = SP + FRAME
|| B .S2 b3 ; Branch to continue in the interrupt handler
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