📄 os_cpu.h
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/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
*
* (c) Copyright 1992-1998, Jean J. Labrosse, Plantation, FL
* All Rights Reserved
*
* 80x86/80x88 Specific code
* LARGE MEMORY MODEL
*
* File : OS_CPU.H
* By : Jean J. Labrosse
*********************************************************************************************************
*/
#ifdef OS_CPU_GLOBALS
#define OS_CPU_EXT
#else
#define OS_CPU_EXT extern
#endif
/*
*********************************************************************************************************
* DATA TYPES
* (Compiler Specific)
*********************************************************************************************************
*/
typedef unsigned char BOOLEAN;
typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
typedef signed char INT8S; /* Signed 8 bit quantity */
typedef unsigned short INT16U; /* Unsigned 16 bit quantity */
typedef signed short INT16S; /* Signed 16 bit quantity */
typedef unsigned int INT32U; /* Unsigned 32 bit quantity */
typedef signed int INT32S; /* Signed 32 bit quantity */
typedef float FP32; /* Single precision floating point */
typedef double FP64; /* Double precision floating point */
typedef unsigned int OS_STK; /* Each stack entry is 32-bit wide */
#define BYTE INT8S /* Define data types for backward compatibility ... */
#define UBYTE INT8U /* ... to uC/OS V1.xx. Not actually needed for ... */
#define WORD INT16S /* ... uC/OS-II. */
#define UWORD INT16U
#define LONG INT32S
#define ULONG INT32U
#define OS_FAR /* Define OS_FAR for the processor (ix86 CPUs) */
typedef struct
{
int integer;
}
REGISTERS ;
/*------------------------------------------------------------------------
THE SP MUST BE ALIGNED ON AN 8-BYTE BOUNDARY.
WHICH means that the framesize has to be a multiple of that
------------------------------------------------------------------------*/
typedef struct
{
void (*Start_Address)(void *Task_Data_Pointer);
REGISTERS
A0 ,
A1 ,
A2 ,
A3 ,
A4 ,
A5 ,
A6 ,
A7 ,
A8 ,
A9 ,
A10 ,
A11 ,
A12 ,
A13 ,
A14 ,
A15 ;
REGISTERS
B0 ,
B1 ,
B2 ,
B3 ,
B4 ,
B5 ,
B6 ,
B7 ,
B8 ,
B9 ,
B10 ,
B11 ,
B12 ,
B13 ,
B14 ,
B15 ;
/* 32 registers */
int
AMR_Adressing_Mode_Register , /* save/restore */
CSR_Control_Status_Register , /* save/restore */
IER_Interrupt_Enable_Register , /* save/restore */
IRP_Interrupt_Return_Pointer ; /* save/restore */
/* 36 registers */
int dummyForAlignment ;
} INITIAL_REGISTER_FRAME;
/* CPU Interrupt Numbers */
#define CPU_INT_RST 0x00
#define CPU_INT_NMI 0x01
#define CPU_INT_RSV1 0x02
#define CPU_INT_RSV2 0x03
#define CPU_INT4 0x04
#define CPU_INT5 0x05
#define CPU_INT6 0x06
#define CPU_INT7 0x07
#define CPU_INT8 0x08
#define CPU_INT9 0x09
#define CPU_INT10 0x0A
#define CPU_INT11 0x0B
#define CPU_INT12 0x0C
#define CPU_INT13 0x0D
#define CPU_INT14 0x0E
#define CPU_INT15 0x0F
#define HostPortInterfaceControlRegister 0x1880000
#define c60_magic 0x95
#define CPLD_MAP0_BASE_ADDR 0x01380000
#define CPLD_MAP1_BASE_ADDR 0x01780000
#ifdef _TMS320C6X
extern cregister volatile unsigned int IER ;
extern volatile unsigned int Always_Enabled_Interrupts ;
extern volatile unsigned int Normally_Enabled_Interrupts ;
static inline void OS_ENTER_CRITICAL(void)
{
IER = Always_Enabled_Interrupts;
asm(" nop 4 ");
}
static inline void OS_EXIT_CRITICAL(void)
{
IER = Normally_Enabled_Interrupts ;
}
#endif
#define OS_TASK_SW() OSCtxSw()
#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory on 80x86 */
/*
*********************************************************************************************************
* GLOBAL VARIABLES
*********************************************************************************************************
*/
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