📄 sst1init3.h
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| (0 & SST_TEX_SEND_CONFIG) \
| (0 & SST_TEX_RESET_FIFO) \
| (0 & SST_TEX_RESET_GRX) \
| (0 << SST_TEX_PALETTE_DEL_SHIFT) \
| (0 << SST_TEX_SEND_CONFIG_SEL_SHIFT) )
#define SST_TREX0INIT1_DEFAULT SST_TREXINIT1_DEFAULT
#define SST_TREX1INIT1_DEFAULT SST_TREXINIT1_DEFAULT
#define SST_TREX2INIT1_DEFAULT SST_TREXINIT1_DEFAULT
/*----------------- SST clutData bits -----------------------*/
#define SST_CLUTDATA_INDEX_SHIFT 24
#define SST_CLUTDATA_RED_SHIFT 16
#define SST_CLUTDATA_GREEN_SHIFT 8
#define SST_CLUTDATA_BLUE_SHIFT 0
/*----------------- SST video setup shifts ------------------*/
#define SST_VIDEO_HSYNC_OFF_SHIFT 16
#define SST_VIDEO_HSYNC_ON_SHIFT 0
#define SST_VIDEO_VSYNC_OFF_SHIFT 16
#define SST_VIDEO_VSYNC_ON_SHIFT 0
#define SST_VIDEO_HBACKPORCH_SHIFT 0
#define SST_VIDEO_VBACKPORCH_SHIFT 16
#define SST_VIDEO_XDIM_SHIFT 0
#define SST_VIDEO_YDIM_SHIFT 16
/*----------------- SST dacData constants -------------------*/
#define SST_DACREG_WMA 0x0
#define SST_DACREG_LUT 0x1
#define SST_DACREG_RMR 0x2
#define SST_DACREG_RMA 0x3
#define SST_DACREG_ICS_PLLADDR_WR 0x4 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_RD 0x7 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_DATA 0x5 /* ICS only */
#define SST_DACREG_ICS_CMD 0x6 /* ICS only */
#define SST_DACREG_ICS_COLORMODE_16BPP 0x50 /* ICS only */
#define SST_DACREG_ICS_COLORMODE_24BPP 0x70 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_VCLK0 0x0 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_VCLK1 0x1 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_VCLK7 0x7 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_VCLK1_DEFAULT 0x55 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_VCLK7_DEFAULT 0x71 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_GCLK0 0xa /* ICS only */
#define SST_DACREG_ICS_PLLADDR_GCLK1 0xb /* ICS only */
#define SST_DACREG_ICS_PLLADDR_GCLK1_DEFAULT 0x79 /* ICS only */
#define SST_DACREG_ICS_PLLADDR_CTRL 0xe /* ICS only */
#define SST_DACREG_ICS_PLLCTRL_CLK1SEL BIT(4)
#define SST_DACREG_ICS_PLLCTRL_CLK0SEL BIT(5)
#define SST_DACREG_ICS_PLLCTRL_CLK0FREQ 0x7
#define SST_DACREG_INDEXADDR SST_DACREG_WMA
#define SST_DACREG_INDEXDATA SST_DACREG_RMR
#define SST_DACREG_INDEX_RMR 0x0
#define SST_DACREG_INDEX_CR0 0x1
#define SST_DACREG_INDEX_MIR 0x2
#define SST_DACREG_INDEX_MIR_ATT_DEFAULT 0x84 /* AT&T */
#define SST_DACREG_INDEX_MIR_TI_DEFAULT 0x97 /* TI */
#define SST_DACREG_INDEX_DIR 0x3
#define SST_DACREG_INDEX_DIR_ATT_DEFAULT 0x9 /* AT&T */
#define SST_DACREG_INDEX_DIR_TI_DEFAULT 0x9 /* TI */
#define SST_DACREG_INDEX_TST 0x4
#define SST_DACREG_INDEX_CR1 0x5
#define SST_DACREG_INDEX_CC 0x6
#define SST_DACREG_INDEX_AA0 0xff /* can't access */
#define SST_DACREG_INDEX_AA1 0xff /* can't access */
#define SST_DACREG_INDEX_AB0 0xff /* can't access */
#define SST_DACREG_INDEX_AB1 0xff /* can't access */
#define SST_DACREG_INDEX_AB2 0xff /* can't access */
#define SST_DACREG_INDEX_AC0 0x48
#define SST_DACREG_INDEX_AC1 0x49
#define SST_DACREG_INDEX_AC2 0x4a
#define SST_DACREG_INDEX_AD0 0x4c
#define SST_DACREG_INDEX_AD1 0x4d
#define SST_DACREG_INDEX_AD2 0x4e
#define SST_DACREG_INDEX_BA0 0xff /* can't access */
#define SST_DACREG_INDEX_BA1 0xff /* can't access */
#define SST_DACREG_INDEX_BB0 0xff /* can't access */
#define SST_DACREG_INDEX_BB1 0xff /* can't access */
#define SST_DACREG_INDEX_BB2 0xff /* can't access */
#define SST_DACREG_INDEX_BC0 0xff /* can't access */
#define SST_DACREG_INDEX_BC1 0xff /* can't access */
#define SST_DACREG_INDEX_BC2 0xff /* can't access */
#define SST_DACREG_INDEX_BD0 0x6c
#define SST_DACREG_INDEX_BD1 0x6d
#define SST_DACREG_INDEX_BD2 0x6e
#define SST_DACREG_CR0_INDEXED_ADDRESSING BIT(0)
#define SST_DACREG_CR0_8BITDAC BIT(1)
#define SST_DACREG_CR0_SLEEP BIT(3)
#define SST_DACREG_CR0_COLOR_MODE_SHIFT 4
#define SST_DACREG_CR0_COLOR_MODE (0xF<<SST_DACREG_CR0_COLOR_MODE_SHIFT)
#define SST_DACREG_CR0_COLOR_MODE_16BPP (0x3<<SST_DACREG_CR0_COLOR_MODE_SHIFT)
#define SST_DACREG_CR0_COLOR_MODE_24BPP (0x5<<SST_DACREG_CR0_COLOR_MODE_SHIFT)
#define SST_DACREG_CR1_BLANK_PEDASTAL_EN BIT(4)
#define SST_DACREG_CC_BCLK_SEL_SHIFT 0
#define SST_DACREG_CC_BCLK_SELECT_BD BIT(3)
#define SST_DACREG_CC_ACLK_SEL_SHIFT 4
#define SST_DACREG_CC_ACLK_SELECT_AD BIT(7)
#define SST_DACREG_CLKREG_MSHIFT 0
#define SST_DACREG_CLKREG_PSHIFT 6
#define SST_DACREG_CLKREG_NSHIFT 0
#define SST_DACREG_CLKREG_LSHIFT 4
#define SST_DACREG_CLKREG_IBSHIFT 0
#define SST_FBI_DACTYPE_ATT 0
#define SST_FBI_DACTYPE_ICS 1
#define SST_FBI_DACTYPE_TI 2
/* Definitions for parsing voodoo.ini file */
#define DACRDWR_TYPE_WR 0
#define DACRDWR_TYPE_RDMODWR 1
#define DACRDWR_TYPE_RDNOCHECK 2
#define DACRDWR_TYPE_RDCHECK 3
#define DACRDWR_TYPE_RDPUSH 4
#define DACRDWR_TYPE_WRMOD_POP 5
/* Other useful defines */
#define PCICFG_WR(ADDR, DATA) \
n = DATA; \
if(pciSetConfigData(ADDR, sst1InitDeviceNumber, &n) == FXFALSE) \
return(FXFALSE)
#define PCICFG_RD(ADDR, DATA) \
if(pciGetConfigData(ADDR, sst1InitDeviceNumber, &DATA) == FXFALSE) \
return(FXFALSE)
#define DAC_INDEXWRADDR(ADDR) \
sst1InitDacWr(sstbase, SST_DACREG_INDEXADDR, ADDR)
#define DAC_INDEXWR(DATA) \
sst1InitDacWr(sstbase, SST_DACREG_INDEXDATA, (DATA))
#define DAC_INDEXRD() \
sst1InitDacRd(sstbase, SST_DACREG_INDEXDATA)
/*-----------------------------------------------------------*/
/*
** SST-1 Initialization typedefs
**
*/
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
float freq;
FxU32 clkTiming_M;
FxU32 clkTiming_P;
FxU32 clkTiming_N;
FxU32 clkTiming_L;
FxU32 clkTiming_IB;
} sst1ClkTimingStruct;
typedef struct {
unsigned char type;
unsigned char addr;
FxU32 data;
FxU32 mask;
void *nextRdWr;
} sst1InitDacRdWrStruct;
typedef struct {
FxU32 width;
FxU32 height;
FxU32 refresh;
FxU32 video16BPP;
sst1InitDacRdWrStruct *setVideoRdWr;
void *nextSetVideo;
} sst1InitDacSetVideoStruct;
typedef struct {
FxU32 frequency;
sst1InitDacRdWrStruct *setMemClkRdWr;
void *nextSetMemClk;
} sst1InitDacSetMemClkStruct;
typedef struct {
FxU32 video16BPP;
sst1InitDacRdWrStruct *setVideoModeRdWr;
void *nextSetVideoMode;
} sst1InitDacSetVideoModeStruct;
typedef struct {
char dacManufacturer[100];
char dacDevice[100];
sst1InitDacRdWrStruct *detect;
sst1InitDacSetVideoStruct *setVideo;
sst1InitDacSetMemClkStruct *setMemClk;
sst1InitDacSetVideoModeStruct *setVideoMode;
void *nextDac;
} sst1InitDacStruct;
typedef struct {
char envVariable[100];
char envValue[256];
void *nextVar;
} sst1InitEnvVarStruct;
FX_ENTRY FxU32 * FX_CALL sst1InitMapBoard(FxU32);
FX_ENTRY FxU32 * FX_CALL sst1InitMapBoardDirect(FxU32, FxBool);
FX_ENTRY FxU32 FX_CALL sst1InitNumBoardsInSystem(void);
FX_ENTRY FxBool FX_CALL sst1InitRegisters(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitGamma(FxU32 *, double);
FX_ENTRY FxBool FX_CALL sst1InitGammaRGB(FxU32 *, double, double, double);
FX_ENTRY FxBool FX_CALL sst1InitGammaTable(FxU32 *, FxU32, FxU32 *, FxU32 *, FxU32 *);
// Note: sst1InitVideo() is for compatibility with SST-1 only, and should
// not be used for Voodoo2. Use sst1InitVideoBuffers() instead
FX_ENTRY FxBool FX_CALL sst1InitVideo(FxU32 *, GrScreenResolution_t,
GrScreenRefresh_t, void *);
FX_ENTRY FxBool FX_CALL sst1InitVideoBuffers(FxU32 *, GrScreenResolution_t,
GrScreenRefresh_t, FxU32, FxU32, sst1VideoTimingStruct *);
FX_ENTRY FxBool FX_CALL sst1InitShutdown(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitShutdownSli(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitSli(FxU32 *, FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitGetDeviceInfo(FxU32 *, sst1DeviceInfoStruct *);
FX_ENTRY FxBool FX_CALL sst1InitVideoBorder(FxU32 *, FxU32, FxU32);
/* Miscellaneous routines */
FX_ENTRY void FX_CALL sst1InitWrite32(FxU32 *, FxU32);
FX_ENTRY FxU32 FX_CALL sst1InitRead32(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitIdle(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitIdleNoNOP(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitIdleFBI(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitIdleFBINoNOP(FxU32 *);
FX_ENTRY FxU32 FX_CALL sst1InitReturnStatus(FxU32 *);
FX_ENTRY FxU32 FX_CALL sst1InitDacRd(FxU32 *, FxU32);
FX_ENTRY void FX_CALL sst1InitDacWr(FxU32 *, FxU32, FxU32);
FxBool sst1InitExecuteDacRdWr(FxU32 *, sst1InitDacRdWrStruct *);
FX_ENTRY void FX_CALL sst1InitSetResolution(FxU32 *, sst1VideoTimingStruct *,
FxU32);
FX_ENTRY FxBool FX_CALL sst1InitDacIndexedEnable(FxU32 *, FxU32);
FX_ENTRY FxBool FX_CALL sst1InitGrxClk(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitCalcGrxClk(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitDacDetect(FxU32 *);
FxBool sst1InitDacDetectATT(FxU32 *);
FxBool sst1InitDacDetectTI(FxU32 *);
FxBool sst1InitDacDetectICS(FxU32 *);
FxBool sst1InitDacDetectINI(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitSetGrxClk(FxU32 *, sst1ClkTimingStruct *);
FxBool sst1InitComputeClkParams(float, sst1ClkTimingStruct *);
FxBool sst1InitComputeClkParamsATT(float, sst1ClkTimingStruct *);
FxBool sst1InitComputeClkParamsTI(float, sst1ClkTimingStruct *);
FxBool sst1InitSetGrxClkATT(FxU32 *, sst1ClkTimingStruct *);
FxBool sst1InitSetGrxClkICS(FxU32 *, sst1ClkTimingStruct *);
FxBool sst1InitSetGrxClkINI(FxU32 *, sst1ClkTimingStruct *);
FX_ENTRY FxBool FX_CALL sst1InitSetVidClk(FxU32 *, float);
FxBool sst1InitSetVidClkATT(FxU32 *, sst1ClkTimingStruct *);
FxBool sst1InitSetVidClkICS(FxU32 *, sst1ClkTimingStruct *);
FxBool sst1InitSetVidClkINI(FxU32 *, FxU32, FxU32, FxU32, FxU32);
FxBool sst1InitSetVidMode(FxU32 *, FxU32);
FxBool sst1InitSetVidModeATT(FxU32 *, FxU32);
FxBool sst1InitSetVidModeICS(FxU32 *, FxU32);
FxBool sst1InitSetVidModeINI(FxU32 *, FxU32);
FX_ENTRY FxBool FX_CALL sst1InitCheckBoard(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitGetFbiInfo(FxU32 *, sst1DeviceInfoStruct *);
FX_ENTRY FxBool FX_CALL sst1InitGetTmuInfo(FxU32 *, sst1DeviceInfoStruct *);
FX_ENTRY void FX_CALL sst1InitRenderingRegisters(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitGetTmuMemory(FxU32 *sstbase,
sst1DeviceInfoStruct *info, FxU32 tmu, FxU32 *TmuMemorySize);
FX_ENTRY FxBool FX_CALL sst1InitClearSwapPending(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitVgaPassCtrl(FxU32 *, FxU32);
FxBool sst1InitResetTmus(FxU32 *);
FX_ENTRY FxU32 FX_CALL sst1InitSliDetect(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitVoodooFile(void);
FX_ENTRY char * FX_CALL sst1InitGetenv(char *);
FX_ENTRY FxU32 * FX_CALL sst1InitGetBaseAddr(FxU32);
FxBool sst1InitFillDeviceInfo(FxU32 *, sst1DeviceInfoStruct *);
void sst1InitIdleLoop(FxU32 *, FxBool);
void sst1InitPciFifoIdleLoop(FxU32 *);
void sst1InitClearBoardInfo(void);
FX_ENTRY FxBool FX_CALL sst1InitCaching(FxU32* sstBase, FxBool enableP);
FX_ENTRY void FX_CALL sst1InitPrintInitRegs(FxU32 *);
sst1VideoTimingStruct *sst1InitFindVideoTimingStruct(GrScreenResolution_t,
GrScreenRefresh_t);
FX_ENTRY FxU32 FX_CALL sst1InitMeasureSiProcess(FxU32 *, FxU32);
FX_ENTRY FxBool FX_CALL sst1InitCmdFifo(FxU32 *, FxBool, FxU32 *, FxU32 *,
FxU32 *, FxSet32Proc);
FX_ENTRY FxBool FX_CALL sst1InitCmdFifoDirect(FxU32 *, FxU32, FxU32, FxU32,
FxBool, FxBool, FxSet32Proc);
FX_ENTRY FxBool FX_CALL sst1InitLfbLock(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitLfbLockDirect(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitLfbUnlock(FxU32 *);
FX_ENTRY FxBool FX_CALL sst1InitLfbUnlockDirect(FxU32 *);
FxU32 sst1InitConvertRefreshRate( FxU32 );
FX_ENTRY FxBool FX_CALL sst1InitMonitorDetect(FxU32 *);
#ifdef __cplusplus
}
#endif
/* Info/Print routines */
#ifdef INIT_OUTPUT
#ifdef __cplusplus
extern "C" {
#endif
FX_ENTRY void FX_CALL sst1InitPrintf(const char *, ...);
#ifdef __cplusplus
}
#endif
#ifndef _FILE_DEFINED
#include <stdio.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SST1INIT_ALLOCATE
FILE *sst1InitMsgFile = stdout;
#else
extern FILE *sst1InitMsgFile;
#endif
#ifdef __cplusplus
}
#endif
#endif
/* Maximum number of SST-1 boards supported in system */
#define SST1INIT_MAX_BOARDS 16
/* Maximum number of read pushes in "voodoo.ini" file */
#define DACRDWR_MAX_PUSH 16
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SST1INIT_ALLOCATE
static char headersIdent[] = "@#%Voodoo2 InitHeaders $Revision: 47 $";
FxBool sst1InitUseVoodooFile = FXFALSE;
sst1InitEnvVarStruct *envVarsBase = (sst1InitEnvVarStruct *) NULL;
sst1InitDacStruct *dacStructBase = (sst1InitDacStruct *) NULL;
sst1InitDacStruct *iniDac = (sst1InitDacStruct *) NULL;
sst1InitDacSetVideoStruct *iniVideo = (sst1InitDacSetVideoStruct *) NULL;
sst1InitDacSetMemClkStruct *iniMemClk = (sst1InitDacSetMemClkStruct *) NULL;
FxU32 iniStack[DACRDWR_MAX_PUSH];
int iniStackPtr = 0;
sst1DeviceInfoStruct *sst1CurrentBoard;
FxU32 sst1InitDeviceNumber;
sst1DeviceInfoStruct sst1BoardInfo[SST1INIT_MAX_BOARDS];
FxU32 boardsInSystem;
FxU32 boardsInSystemReally;
FxU32 initIdleEnabled = 1;
const PciRegister SST1_PCI_CFG_SCRATCH = { 0x50, 4, READ_WRITE };
const PciRegister SST1_PCI_SIPROCESS = { 0x54, 4, READ_WRITE };
#else
extern FxBool sst1InitUseVoodooFile;
extern sst1InitEnvVarStruct *envVarsBase;
extern sst1InitDacStruct *dacStructBase;
extern sst1InitDacStruct *iniDac;
extern sst1InitDacSetVideoStruct *iniVideo;
extern sst1InitDacSetMemClkStruct *iniMemClk;
extern FxU32 iniStack[];
extern int iniStackPtr;
extern sst1DeviceInfoStruct *sst1CurrentBoard;
extern FxU32 sst1InitDeviceNumber;
extern sst1DeviceInfoStruct sst1BoardInfo[SST1INIT_MAX_BOARDS];
extern FxU32 boardsInSystem;
extern FxU32 boardsInSystemReally;
extern FxU32 initIdleEnabled;
extern PciRegister SST1_PCI_CFG_SCRATCH;
extern PciRegister SST1_PCI_SIPROCESS;
#endif /* SST1INIT_ALLOCATE */
#ifdef __3Dfx_PCI_CFG__
/* This is really ugly, but it makes us happy w/ the top of the tree
* pci library which is happier than Gary's library.
*/
#define SST1_PCI_INIT_ENABLE PCI_SST1_INIT_ENABLE
#define SST1_PCI_BUS_SNOOP0 PCI_SST1_BUS_SNOOP_0
#define SST1_PCI_BUS_SNOOP1 PCI_SST1_BUS_SNOOP_1
#define SST1_PCI_CFG_STATUS PCI_SST1_CFG_STATUS
#else /* !__3Dfx_PCI_CFG__ */
#define SST1_PCI_BUS_SNOOP0 SST1_PCI_BUS_SNOOP_0
#define SST1_PCI_BUS_SNOOP1 SST1_PCI_BUS_SNOOP_1
#endif /* !__3Dfx_PCI_CFG__ */
#ifdef __cplusplus
}
#endif
#ifdef SST1INIT_VIDEO_ALLOCATE
/* SST1INIT_VIDEO_ALLOCATE is only #defined in video.c
Define useful clock and video timings
Clocks generated are follows:
Clock Freq. (MHz) =
[14.318 * (clkTiming_M+2)] / [(clkTiming_N+2) * (2^clkTiming_P)]
Solving for clkTiming_M yields:
clkTiming_M =
[ [(Clock Freq (Mhz)) * (clkTiming_N+2) * (2^clkTiming_P)] / 14.318 ] - 2
NOTE: [14.318 * (clkTiming_M+2)] / (clkTiming_N+2) should be between
120 and 240
NOTE: Max. M is 127
NOTE: Max. N is 31
NOTE: Max. P is 3
NOTE: Max. L is 15
NOTE: Max. IB is 15
*/
sst1VideoTimingStruct SST_VREZ_320X200_70 = {
96, /* hSyncOn */
704, /* hSyncOff */
2, /* vSyncOn */
447, /* vSyncOff */
48, /* hBackPorch */
35, /* vBackPorch */
320, /* xDimension */
200, /* yDimension */
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