📄 reset.s
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;******************************************************************;
; This is the boot routine for the MC68VZ328 ADS board. Product
; engineers should examine all the configurations carefully and
; change them according to their system requirements.
;******************************************************************;
MON_BOOT .equ ___reset ; Boot entry point
MON_STACKTOP .equ $4100 ; Initial stack
M328BASE .equ $FFFFF000 ; Base address for system registers
; SIM28 System Configuration Registers
SCR .equ (M328BASE+$000)
; Chip Select Registers
; CS Group Base Registers
GRPBASEA .equ (M328BASE+$100)
GRPBASEB .equ (M328BASE+$102)
GRPBASEC .equ (M328BASE+$104)
GRPBASED .equ (M328BASE+$106)
; CS Registers
CSA .equ (M328BASE+$110)
CSB .equ (M328BASE+$112)
CSC .equ (M328BASE+$114)
CSD .equ (M328BASE+$116)
CSCR .equ (M328BASE+$10A)
DRAMCFG .equ (M328BASE+$C00)
DRAMMC .equ (M328BASE+$C00)
DRAMCTL .equ (M328BASE+$C02)
DRAMC .equ (M328BASE+$C02)
SDCTRL .equ (M328BASE+$C04)
EMUCS .equ (M328BASE+$118)
CSCTR .equ (M328BASE+$150)
; PLL Registers
PLLCR .equ (M328BASE+$200) ; Control Reg
PLLFSR .equ (M328BASE+$202) ; Freq Select Reg
PLLTSR .equ (M328BASE+$204) ; Test Reg
; Power Control Registers
PCTLR .equ (M328BASE+$206) ; Control Reg
; Interrupt Registers
IVR .equ (M328BASE+$300) ; Interrupt Vector Reg
ICR .equ (M328BASE+$302) ; Interrupt Control Reg
IMR .equ (M328BASE+$304) ; Interrupt Mask Reg
ISR .equ (M328BASE+$30C) ; Interrupt Status Reg
IPR .equ (M328BASE+$310) ; Interrupt Pending Reg
; PIO Registers
; Port A Registers
PADIR .equ (M328BASE+$400) ; Direction Reg
PADATA .equ (M328BASE+$401) ; Data Reg
PAPUEN .equ (M328BASE+$402) ; Pullup Enable Reg
; Port B Registers
PBDIR .equ (M328BASE+$408) ; Direction Reg
PBDATA .equ (M328BASE+$409) ; Data Reg
PBPUEN .equ (M328BASE+$40A) ; Pullup Enable Reg
PBSEL .equ (M328BASE+$40B) ; Select Reg
; Port C Registers
PCDIR .equ (M328BASE+$410) ; Direction Reg
PCDATA .equ (M328BASE+$411) ; Data Reg
PCPUEN .equ (M328BASE+$412) ; Pullup Enable Reg
PCPDEN .equ (M328BASE+$412) ; Pull-down Enable Reg
PCSEL .equ (M328BASE+$413) ; Select Reg
; Port D Registers
PDDIR .equ (M328BASE+$418) ; Direction Reg
PDDATA .equ (M328BASE+$419) ; Data Reg
PDPUEN .equ (M328BASE+$41A) ; Pullup Enable Reg
PDSEL .equ (M328BASE+$41B) ; Select Reg
PDPOL .equ (M328BASE+$41C) ; Polarity Reg
PDIRQEN .equ (M328BASE+$41D) ; IRQ Enable Reg
PDIRQEDGE .equ (M328BASE+$41F) ; IRQ Edge Reg
; Port E Registers
PEDIR .equ (M328BASE+$420) ; Direction Reg
PEDATA .equ (M328BASE+$421) ; Data Reg
PEPUEN .equ (M328BASE+$422) ; Pullup Enable Reg
PESEL .equ (M328BASE+$423) ; Select Reg
; Port F Registers
PFDIR .equ (M328BASE+$428) ; Direction Reg
PFDATA .equ (M328BASE+$429) ; Data Reg
PFPUEN .equ (M328BASE+$42A) ; Pullup Enable Reg
PFSEL .equ (M328BASE+$42B) ; Select Reg
; Port G Registers
PGDIR .equ (M328BASE+$430) ; Direction Reg
PGDATA .equ (M328BASE+$431) ; Data Reg
PGPUEN .equ (M328BASE+$432) ; Pullup Enable Reg
PGSEL .equ (M328BASE+$433) ; Select Reg
PKSEL .equ (M328BASE+$443) ; Select Reg
PMSEL .equ (M328BASE+$44B) ; Select Reg
; PWM Registers
PWMC .equ (M328BASE+$500) ; Control Reg
PWMS .equ (M328BASE+$502) ; Sample Reg
PWMCNT .equ (M328BASE+$504) ; Counter
; Timer Registers
; Timer 1 Registers
TCTL1 .equ (M328BASE+$600) ; Control Reg
TPRER1 .equ (M328BASE+$602) ; Prescalar Reg
TCMP1 .equ (M328BASE+$604) ; Compare Reg
TCR1 .equ (M328BASE+$606) ; Capture Reg
TCN1 .equ (M328BASE+$608) ; Counter
TSTAT1 .equ (M328BASE+$60A) ; Status Reg
; Watchdog Registers
WCR .equ (M328BASE+$B0A) ; Control Reg
; SPI Registers
; SPI Master Registers
SPIMDATA .equ (M328BASE+$800) ; Control/Status Reg
SPIMCONT .equ (M328BASE+$802) ; Data Reg
; UART Registers
USTCNT .equ (M328BASE+$900) ; Status Control Reg
UBAUD .equ (M328BASE+$902) ; Baud Control Reg
UARTRX .equ (M328BASE+$904) ; Rx Reg
UARTTX .equ (M328BASE+$906) ; Tx Reg
UARTMISC .equ (M328BASE+$908) ; Misc Reg
UARTNIPR .equ (M328BASE+$90A) ; Non-Integer Prescalar Reg
; LCDC Registers
LSSA .equ (M328BASE+$A00) ; Screen Start Addr Reg
LVPW .equ (M328BASE+$A05) ; Virtual Page Width Reg
LXMAX .equ (M328BASE+$A08) ; Screen Width Reg
LYMAX .equ (M328BASE+$A0A) ; Screen Height Reg
LCXP .equ (M328BASE+$A18) ; Cursor X Position
LCYP .equ (M328BASE+$A1A) ; Cursor Y Position
LCWCH .equ (M328BASE+$A1C) ; Cursor Width & Height Reg
LBLKC .equ (M328BASE+$A1F) ; Blink Control Reg
LPICF .equ (M328BASE+$A20) ; Panel Interface Config Reg
LPOLCF .equ (M328BASE+$A21) ; Polarity Config Reg
LACDRC .equ (M328BASE+$A23) ; ACD (M) Rate Control Reg
LPXCD .equ (M328BASE+$A25) ; Pixel Clock Divider Reg
LCKCON .equ (M328BASE+$A27) ; Clocking Control Reg
LRRA .equ (M328BASE+$A29) ; Last Buffer Addr Reg
LOTCR .equ (M328BASE+$A2B) ; Octet Terminal Count Reg
LPOSR .equ (M328BASE+$A2D) ; Panning Offset Reg
LFRCM .equ (M328BASE+$A31) ; Frame Rate Control Mod Reg
LGPMR .equ (M328BASE+$A32) ; Gray Palette Mapping Reg
LIRQR .equ (M328BASE+$A34) ; Interrupt Control Reg
; RTC Registers
RTCHMSR .equ (M328BASE+$B00) ; Hrs Mins Secs Reg
RTCALM0R .equ (M328BASE+$B04) ; Alarm Register 0
RTCDAY .equ (M328BASE+$B08) ; RTC date reg
RTCWD .equ (M328BASE+$B0A) ; RTC watch dog timer reg
RTCCTL .equ (M328BASE+$B0C) ; Control Reg
RTCISR .equ (M328BASE+$B0E) ; Interrupt Status Reg
RTCIENR .equ (M328BASE+$B10) ; Interrupt Enable Reg
RSTPWCH .equ (M328BASE+$B12) ; Stopwatch Minutes
; ICEM registers
ICEMACR .equ (M328BASE+$D00)
ICEMAMR .equ (M328BASE+$D04)
ICEMCCR .equ (M328BASE+$D08)
ICEMCMR .equ (M328BASE+$D0A)
ICEMCR .equ (M328BASE+$D0C)
ICEMSR .equ (M328BASE+$D0E)
******************************************************************************
* RESET OPTIONS
******************************************************************************
.section .reset
rom_base:
;-- SECTION rom_reset - SP, start addr & space for Exception Vectors
.DC.L MON_STACKTOP ; stack pointer
.DC.L MON_BOOT ; program counter
.skip (62*4) ; space for Motorola defined Exception Vectors
.skip (192*4) ; space for the 192 User defined Exception Vectors
.global ___reset
___reset:
;************************************************
;* System initialization *
;************************************************
move.b #$18,SCR ; Disable Double Map
;************************************************
;* Primary boot image is at start of flash.
;* Secondary boot image is at start+0x10000.
;* If this is the primary image and PD2 is low,
;* boot alternate image.
;************************************************
lea.l 0(PC), A0 ; get PC
move.l A0, D0
and.l #$10000, D0 ; is this secondary image?
bne.s boot_trk ; if so, don't check switch,
; just boot this image
ori.b #$0F,PDSEL
move.b #$03,PDDIR
move.b #$FF,PDPUEN
move.b PDDATA,D0
andi.b #$04,D0
bne.s boot_trk ; if PD2 high, boot this image
move.l $01010000, SP ; otherwise boot alternate image
move.l $01010004, A0
jmp (A0)
;************************************************
; Booting MetroTRK
;************************************************
boot_trk:
move.b #$9,PGSEL ; config PG0/DTACK to GPI/O,input
move.w #$2400,PLLCR ; ??MHz Sysclk, enable clko
move.l #MON_STACKTOP,A7 ; Install stack pointer
move.w #$2700,sr ; mask off all interrupts
move.w #$00,RTCWD ; disable watch dog
move.w #$08,ICEMCR ; disable ICEM vector hardmap
move.w #$07,ICEMSR ; clear level 7 interrupt
;******************************
;* Port Initialization *
;******************************
move.b #$03,PFSEL ; select A23-A20, CLKO, CSA1
move.b #$00,PBSEL ; Config port B for chip select A,B,C and D
move.b #$00,PESEL ; select *DWE
move.b #$F1,PKSEL
move.b #$00,PMSEL
;******************************
;* Chip Select initialization *
;******************************
;**********************
; Flash
;**********************
move.w #$0800,GRPBASEA ; GROUPA BASE(FLASH), Start add.=0x1000000
move.w #$0199,CSA ;
;***************************************
; SDRAM 64M-bit, Single Band, Latency 2
;***************************************
move.w #$0000,GRPBASED
move.w #$0281,CSD
move.w #$0040,CSCR ; Chip Sel Control Reg
move.w #$0000,DRAMC ; Disable DRAM Controller
move.w #$C03F,SDCTRL
move.w #$4020,DRAMMC
move.w #$8000,DRAMC
clr.w d0
delay:
addi.w #1,d0
cmp.w #$FFFF,d0
bne delay
move.w #$C83F,SDCTRL ; issue precharge comm
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
move.w #$D03F,SDCTRL ; enable refresh
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
move.w #$D43F,SDCTRL ; issue mode command
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
;************************************************
;* End of System initialization *
;************************************************
clr.l d0
clr.l d1
clr.l d2
clr.l d3
clr.l d4
clr.l d5
clr.l d6
clr.l d7
;**********************************************
;* LCD Initization Code *
;**********************************************
move.b #0,PCSEL
move.b #0,PCPDEN
move.l #$100403E,LSSA
move.w #160,LXMAX
move.w #239,LYMAX
move.b #10,LVPW
move.b #$08,LPICF
move.b #$01,LPOLCF
move.b #$00,LACDRC
move.b #$02,LPXCD
move.b #$14,LRRA
move.b #$00,LPOSR
move.b #$00,LCKCON ; disable LCDC
move.b #$80,LCKCON ; enable LCDC, 0ws, 16-bit
;**********************************************************************
;
; Program Interrupt Controller
;
;**********************************************************************
move.b #$40,IVR
move.l #$007FFFFF,IMR ;enable NMI interrupt
;**********************************************************************
;
; Runtime initialization
;
;**********************************************************************
.extern __start
JMP __start ; jump to MW startup code
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