i82593.h

WaveLAN无线网卡Linux驱动程序

/*
 * Copyright (c) 1997 Carnegie Mellon University.
 * All Rights Reserved.
 *
 * Permission to use, copy, modify, and distribute this software and
 * its documentation is hereby granted (including for commercial or
 * for-profit use), provided that both the copyright notice and this
 * permission notice appear in all copies of the software, derivative
 * works, or modified versions, and any portions thereof, and that
 * both notices appear in supporting documentation, and that credit
 * is given to Carnegie Mellon University in all publications reporting
 * on direct or indirect use of this code or its derivatives.
 *
 * THIS IMPLEMENTATION IS EXPERIMENTAL AND MAY HAVE BUGS, SOME OF WHICH
 * MAY HAVE SERIOUS CONSEQUENCES.  CARNEGIE MELLON PROVIDES THIS SOFTWARE
 * IN ITS "AS IS" CONDITION, AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
 * BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL CARNEGIE
 * MELLON UNIVERSITY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Carnegie Mellon encourages (but does not require) users of this
 * software to return any improvements or extensions that they make,
 * and to grant Carnegie Mellon the rights to redistribute these
 * changes without encumbrance.
 *
 *
 */

#ifndef __82593_H__
#define __82593_H__

#ifdef KERNEL

extern char*  I82593_IRQ[16];

/*
 * This file contains declarations and data structures that are specific
 * to Intel's 82593 Ethernet Controller.
 */

/* ======================================================================
   Port 0 Commands
   ====================================================================== */
#define P0_INT_ACK		0x80

#define P0_STATUS0		0x00	/* 2 bits */
#define P0_STATUS1		0x20
#define P0_STATUS2		0x40
#define P0_STATUS3		0x60

#define P0_CHNL			0x10

#define P0_OPCODE		0x0F	/* 4 bits */

#define P0_NOP			0x00
#define P0_SWITCH_TO_P1		(0x00 | P0_CHNL)
#define P0_IA_SETUP		0x01
#define P0_CONFIGURE		0x02
#define P0_MC_SETUP		0x03
#define P0_TRANSMIT		0x04
#define P0_TDR			0x05
#define P0_DUMP			(0x06 | P0_CHNL)
#define P0_DIAGNOSE		0x07
#define P0_RCV_ENABLE		(0x08 | P0_CHNL)
#define P0_TRANSMIT_NOCRC	0x09
#define P0_RCV_DISABLE		(0x0A | P0_CHNL)
#define P0_STOP_RCV		0x0B
#define P0_RETRANSMIT		0x0C
#define P0_ABORT		0x0D
#define P0_RESET		0x0E

/* ======================================================================
   Port 0 Status
   ====================================================================== */
#define P0_S0_INT		0x80
#define P0_S0_RCV		0x40
#define	P0_S0_EXEC		0x20
#define P0_S0_CHNL		0x10
#define P0_S0_EVENT		0x0F	/* 4 bits */

#define P0_S3_EXEC_STATE	0x03	/* 2 bits */
#define P0_S3_EXEC_CHNL		0x04
/* bit 3 is 0 */
#define P0_S3_RCV_STATE		0x70	/* 3 bits */
#define P0_S3_RCV_CHNL		0x80

/* ======================================================================
   Port 1 Commands
   ====================================================================== */
#define P1_NOP			0x00
#define P1_SWITCH_TO_P0		0x01
#define P1_DISABLE_INT		0x02
#define P1_ENABLE_INT		0x03
#define P1_SET_TS		0x05
#define P1_RST_TS		0x07
#define P1_POWER_DOWN		0x08
#define P1_RST_RING_MGMT	0x0B
#define P1_RESET		0x0E
#define P1_SEL_RESET		0x0F
/* bit 4 is 0 */
#define P1_STATUS4		0x00	/* 2-bit field */
#define P1_STATUS5		0x20
#define P1_STATUS6		0x30
/* bit 7 is 0 */

/* ======================================================================
   Interrupts
   ====================================================================== */
#define IA_SETUP_DONE		P0_IA_SETUP
#define CONFIGURE_DONE		P0_CONFIGURE
#define MC_SETUP_DONE		P0_MC_SETUP
#define TRANSMIT_DONE		P0_TRANSMIT
#define TDR_DONE		P0_TDR
#define DUMP_DONE		0x06
#define DIAGNOSE_PASSED		P0_DIAGNOSE
#define END_OF_FRAME		0x08
#define TRANSMIT_NOCRC_DONE	P0_TRANSMIT_NOCRC
#define RCV_ABORT		0x0A
#define STOP_REG_HIT		0x0B
#define RETRANSMIT_DONE		P0_RETRANSMIT
#define EXECUTION_ABORT		P0_ABORT
#define DIAGNOSE_FAILED		0x0F


/* ======================================================================
   Transmit frame status bits
   ====================================================================== */
#define	TX_NUMCOL		0x0F	/* 4 bits */
#define TX_FRTL			0x10
#define TX_MAX_COL		0x20
#define TX_HRT_BET		0x40
#define TX_DEF			0x80
#define TX_UND_RUN		(0x01 << 8)
#define TX_LST_CTS		(0x02 << 8)
#define TX_LST_CRS		(0x04 << 8)
#define TX_LTCOL		(0x08 << 8)
/* bit 4 is 0 */
#define TX_OK			(0x20 << 8)
/* bit 6 is 0 */
#define TX_COLL			(0x80 << 8)

#define TX_STAT_BITS		((0x10 << 8) | TX_OK | (0x40 << 8))

/* ======================================================================
   Receive frame status bits
   ====================================================================== */
#define	RX_RCLD			0x01
#define RX_IA_MCH		0x02
#define	RX_NAD_MCH		0x04
#define RX_NO_SFD		0x08
/* bit 4 should be 1 */
/* bit 5 should be 1 */
/* bit 6 should be 0 */
#define RX_SRT_FRM		0x80

#define RX_OVRRUN		(0x01 << 8)
/* bit 1 should be 0 */
#define RX_ALG_ERR		(0x04 << 8)
#define RX_CRC_ERR		(0x08 << 8)
#define RX_LEN_ERR		(0x10 << 8)
#define RX_RCV_OK		(0x20 << 8)
/* bit 6 should be 0 */
#define RX_TYP_LEN		(0x80 << 8)

#define RX_STAT_BITS	\
	(0x10 | 0x20 | 0x40 | (0x02 << 8) | RX_RCV_OK | (0x40 << 8))

/* ======================================================================
   Configuration Block
   ====================================================================== */
struct i82593_conf_block {
	u_char fifo_limit    : 4,
	       forgnesi      : 1,
	       fifo_32       : 1,
	       d6mod         : 1,
	       throttle_enb  : 1;

	u_char throttle      : 6,
	       cntrxint      : 1,
               contin        : 1;

	u_char addr_len      : 3,
	       acloc         : 1,
	       preamb_len    : 2,
	       loopback      : 2;

	u_char lin_prio      : 3,
	       tbofstop      : 1,
	       exp_prio      : 3,
	       bof_met       : 1;

	u_char               : 4,
	       ifrm_spc      : 4;

	u_char               : 5,
	       slottim_low   : 3;

	u_char slottim_hi    : 3,       
		             : 1,
	       max_retr      : 4;

	u_char prmisc        : 1,       
	       bc_dis        : 1,
		             : 1,
	       crs_1         : 1,
	       ocrc_ins      : 1,
	       rc_1632       : 1, 
		             : 1,
	       crs_cdt       : 1;

	u_char cs_filter     : 3,       
	       crs_src       : 1,
	       cd_filter     : 3,
		             : 1;

	u_char               : 2,
	       min_fr_len    : 6;

	u_char lng_typ       : 1,       
	       lng_fld       : 1,
	       rxcrc_xf      : 1,
	       artx          : 1,
	       sarec         : 1,
	       tx_jabber     : 1,
	       hash_1        : 1,
	       lbpkpol       : 1;

	u_char               : 6,
	       fdx           : 1, 
		             : 1;

	u_char dummy_6       : 6,       /* supposed to be ones */
	       mult_ia       : 1,
	       dis_bof       : 1;

	u_char dummy_1       : 1,       /* supposed to be one */
	       tx_ifs_retrig : 2,
	       mc_all        : 1,
	       rcv_mon       : 2,
	       frag_acpt     : 1,
	       tstrttrs      : 1;

	u_char fretx         : 1,
	       runt_eop      : 1,
	       hw_sw_pin     : 1,
	       big_endn      : 1,
	       syncrqs       : 1,
	       sttlen        : 1,
	       tx_eop        : 1,
	       rx_eop        : 1;

	u_char rbuf_size     : 5,
	       rcvstop       : 1,
		             : 2;
};

struct i82593_conf {
	u_char byte_count_low;
	u_char byte_count_high;
	union {
		u_char bytes[16];
		struct i82593_conf_block cfgblock;
	} data;
};

#endif /* KERNEL */

struct I82593_stats {
  /* Transmit Status Info */
  u_int32_t             txcnt;		/* Transmit Counter */
  u_int32_t             txok;		/* Transmit executed OK */

  u_int32_t             numcol;		/* Number of collisions */
  u_int32_t             frtl;		/* Frame too long */
  u_int32_t		maxcol;		/* Max collisions reached */
  u_int32_t		hrtbet;		/* Heart beat */
  u_int32_t             txdef;		/* Transmit Deferred */
  u_int32_t             undrun;		/* Under Run */
  u_int32_t             lostcts;	/* CTS lost during transmission */
  u_int32_t             lostcrs;	/* CRS lost during transmission */
  u_int32_t		ltcol;		/* Late collision */
  u_int32_t             col;		/* Transmissions failed due to col */

  /* Receive Status Info */
  u_int32_t             rxcnt;		/* Receive Counter */
  u_int32_t             rxok;		/* Frame received OK */

  u_int32_t             rcvcld;		/* Collision detected */
  u_int32_t             iamch;		/* Address match */
  u_int32_t             nadmch;		/* No address match */
  u_int32_t             nosfd;		/* No start of frame delimeter */
  u_int32_t             srtfrm;		/* Short frame */
  u_int32_t             overrun;	/* DMA did not keep up */
  u_int32_t             algerr;		/* Alignment error */
  u_int32_t             crcerr;		/* CRC error */
  u_int32_t             lenerr;		/* Length error */

  /* Other */
  u_int32_t             stopreg;	/* Stop Reg Hit */
  u_int32_t		rexmit;		/* Retransmission count */
  u_int32_t		irqcnt;		/* Receive Interrupts */
};
#define	sc_txcnt	sc_stats.txcnt
#define sc_txok		sc_stats.txok

#define	sc_numcol	sc_stats.numcol
#define	sc_frtl		sc_stats.frtl
#define sc_maxcol	sc_stats.maxcol
#define sc_hrtbet	sc_stats.hrtbet
#define	sc_txdef	sc_stats.txdef
#define sc_undrun	sc_stats.undrun
#define sc_lostcts	sc_stats.lostcts
#define sc_lostcrs	sc_stats.lostcrs
#define sc_ltcol	sc_stats.ltcol
#define sc_col		sc_stats.col

#define sc_rxcnt	sc_stats.rxcnt
#define sc_rxok		sc_stats.rxok
#define sc_rcvcld	sc_stats.rcvcld
#define sc_iamch	sc_stats.iamch
#define sc_nadmch	sc_stats.nadmch
#define sc_nosfd	sc_stats.nosfd
#define sc_srtfrm	sc_stats.srtfrm
#define sc_overrun	sc_stats.overrun
#define sc_algerr	sc_stats.algerr
#define sc_crcerr	sc_stats.crcerr
#define sc_lenerr	sc_stats.lenerr

#define sc_stopreg	sc_stats.stopreg
#define sc_rexmit	sc_stats.rexmit
#define sc_irqcnt	sc_stats.irqcnt

#define i82593_reset_stats(sc)						\
  {									\
    (sc)->sc_txcnt   = 0;  (sc)->sc_txok    = 0; (sc)->sc_numcol  = 0;	\
    (sc)->sc_frtl    = 0;  (sc)->sc_maxcol  = 0; (sc)->sc_hrtbet  = 0;	\
    (sc)->sc_txdef   = 0;  (sc)->sc_undrun  = 0; (sc)->sc_lostcts = 0;	\
    (sc)->sc_lostcrs = 0;  (sc)->sc_ltcol   = 0; (sc)->sc_col     = 0;	\
									\
    (sc)->sc_rxcnt   = 0;  (sc)->sc_rxok    = 0; (sc)->sc_rcvcld  = 0;	\
    (sc)->sc_iamch   = 0;  (sc)->sc_nadmch  = 0; (sc)->sc_nosfd   = 0;	\
    (sc)->sc_srtfrm  = 0;  (sc)->sc_overrun = 0; (sc)->sc_algerr  = 0;	\
    (sc)->sc_crcerr  = 0;  (sc)->sc_lenerr  = 0;			\
									\
    (sc)->sc_stopreg = 0;  (sc)->sc_rexmit  = 0; (sc)->sc_irqcnt  = 0;	\
  }

#endif /* __82593_H__ */