📄 if_wlp_ir.h
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/* * Copyright (c) 1997 Carnegie Mellon University. * All Rights Reserved. * * Permission to use, copy, modify, and distribute this software and * its documentation is hereby granted (including for commercial or * for-profit use), provided that both the copyright notice and this * permission notice appear in all copies of the software, derivative * works, or modified versions, and any portions thereof, and that * both notices appear in supporting documentation, and that credit * is given to Carnegie Mellon University in all publications reporting * on direct or indirect use of this code or its derivatives. * * THIS IMPLEMENTATION IS EXPERIMENTAL AND MAY HAVE BUGS, SOME OF WHICH * MAY HAVE SERIOUS CONSEQUENCES. CARNEGIE MELLON PROVIDES THIS SOFTWARE * IN ITS "AS IS" CONDITION, AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, * BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL CARNEGIE * MELLON UNIVERSITY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Carnegie Mellon encourages (but does not require) users of this * software to return any improvements or extensions that they make, * and to grant Carnegie Mellon the rights to redistribute these * changes without encumbrance. * * */#ifndef __IF_WLP_IR_H__#define __IF_WLP_IR_H__struct wlp_softc;/* ====================================================================== Function Prototypes ====================================================================== */int rwprobe(struct isa_device*);int rwconfig(struct wlp_softc*);int TestRAM(struct wlp_softc*);/* * Definitions for the Alliston III *//* Port 0 - access to the 82593 *//* Port 1 - unused *//* Port 2 - Receive DMA Lo Byte *//* Port 3 - Receive DMA Hi Byte *//* Port 4 - Transmit DMA Lo Byte *//* Port 5 - Transmit DMA Hi Byte */#define RW_ResetTXDMA() \ IOWrite1(0x04, 0x00); IOWrite1(0x05, 0x00); \ IOWrite1(0x09, (IORead1(0x09) & P9_RXBUF)); #define RW_ResetRXDMA() \ IOWrite1(0x02, 0x00); IOWrite1(0x03, 0x00); \ IOWrite1(0x09, (IORead1(0x09) & P9_TXBUF));/* Port 6 - General Purpose Timer *//* Port 7 - Interrput Control Port */#define P7_IRQ_BLOCK 0x80#define P7_CARRIER_SENSE 0x40#define P7_CIRQ_ENABLE 0x20#define P7_CIRQ 0x10#define P7_RESERVED1 0x08#define P7_RESERVED2 0x04#define P7_TIRQ_ENABLE 0x02#define P7_TIRQ 0x01/* Port 8 - Collision Avoidance Port */#define P8_RESET 0x80#define P8_RESERVED1 0x40#define P8_RAM_ROM 0x20#define P8_CA_ENABLE 0x10#define P8_IFS_TIME 0x0F /* 4-bit field */#define IFS_TIME 0x06/* Port 9 - Page Control Port */#define P9_TXBUF 0xF0 /* 4-bit field */#define P9_RXBUF 0x0F /* 4-bit field *//* Port 10 - Collision Avoidance Timer Port */#define P10_CASEED 0xFF /* 8-bit field *//* Port 11 - ISA Switch and IRQ Port */#define P11_ADDR 0xF0 /* 4-bit field */#define P11_IO 0x0E /* 3-bit field */#define P11_RFU 0x01/* Port 12 - Serial Data Port */#define P12_RESERVED1 0x80#define P12_SERIAL_CLOCK 0x40#define P12_SERIAL_DATA_DRIVE 0x20#define P12_ISA_IRQ 0x10#define P12_TRANSCEIVER_ENABLE 0x08#define P12_TRANSCEIVER_DETECT 0x04#define P12_RESERVED2 0x02#define P12_RESERVED3 0x01/* ====================================================================== DEFINES ====================================================================== */#define RW_IOSIZE 0x0010 /* 16 bytes of IO space */#define RW_MSIZE 0x2000 /* 8k memory window */#define RW_PGSIZE 0x0400 /* 1k pages */#define RW_TXBUFSIZE 0x4000 /* 16k */#define RW_RXBUFSIZE 0x4000 /* 16k */#define RW_TXWINDOW 0x1000 /* 4k window */#define RW_RXWINDOW 0x1000 /* 4k window *//* ====================================================================== MACROS ====================================================================== */#define Alliston_HStat(b) \ { \ printf("********** Alliston Port Status **********\n"); \ printf("Port 0: %2x, Port 1: %2x, Port 2: %2x, Port 3: %2x\n", \ inb(b), 0, inb((b) + 0x02), inb((b) + 0x03)); \ printf("Port 4: %2x, Port 5: %2x, Port 6: %2x, Port 7: %2x\n", \ inb((b) + 0x04), inb((b) + 0x05), inb((b) + 0x06), inb((b) + 0x07)); \ printf("Port 8: %2x, Port 9: %2x, Port 10: %2x, Port 11: %2x\n", \ inb((b) + 0x08), inb((b) + 0x09), inb((b) + 0x0A), inb((b) + 0x0B)); \ printf("Port 12: %2x, Port 13: %2x, Port 14: %2x, Port 15: %2x\n", \ inb((b) + 0xC), 0, 0, 0); \ }#define DUMP_CONFIG(sc) \ ifx_dump(sc); \ if( I82593_wait(sc, I82593_DUMP) != (I82593_DUMP | 0xB0) ) \ { \ printf("Dump of the Intel 82593 failed!\n"); \ } \ printf("\nIntel 82593 Dump\n"); \ dump_bytes(sc->sc_maddr, 72);#endif /* __IF_WLP_IR_H__ */
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