📄 uart.asm
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*********************************************************************************
* UART program , communicating with PC
* WRITED BY Baiyangong
* DATA: 4/6/2004
*********************************************************************************
.mmregs
.global _main
.global UART_INT
_main:
;UART regs address start at 0x4000
*********************************************************************************
;Register Selection Table
;-------------------------------------------------------------------------------------
; DLAB | A2 | A1 | A0 | Registers |
; 0 | 0 | 0 | 0 | Rceciver Buffer(Read) , Transmitter holding register(write) |
; 0 | 0 | 0 | 1 | Interrupt enable register |
; x | 0 | 1 | 0 | Interrupt Identification register(Read only) |
; x | 0 | 1 | 0 | FIFO control register (write) |
; x | 0 | 1 | 1 | Line Control register |
; x | 1 | 0 | 0 | Modem control register |
; x | 1 | 0 | 1 | Line sratus register |
; x | 1 | 1 | 0 | Modem status register |
; x | 1 | 1 | 1 | Scratch register |
; 1 | 0 | 0 | 0 | Divisor latch(LSB) |
; 1 | 0 | 0 | 1 | Divesor latch(MSB) |
*-------------------------------------------------------------------------------------
;DLAB is the MSB of LCR , before initiation 550 ,must set DLAB to setup DIVISION
;so the access DLAB address is 0x4003
;the A0->A2 can access the UART
**********************************************************************************
.include "subfunction.inc"
;define macro
.include "subfunction2.inc"
;define macro
.include "init_5410.inc"
;define the initial value of cpu and peripheral registers
.include "TL16C550C.inc"
;Definition of TL16C550C
.include "Address_peripheral.inc"
;define the peripheral address
.text
;=============================================================
; system initiation
;=============================================================
INIT_CPU
INIT_PERIPHERAL
;=============================================================
; UART initiation
;=============================================================
STM #TL_IER , AR1
PORTW AR1 , IER
NOP
NOP
NOP
NOP
;IER init
STM #TL_FCR , AR1
PORTW AR1 , FCR
NOP
NOP
NOP
NOP
;FCR init
STM #0x0080 , AR1
PORTW AR1 , LCR
NOP
NOP
NOP
NOP
STM #0x0018 , AR1
PORTW AR1 , DLSB
NOP
NOP
NOP
NOP
;set Division MSB
STM #0x0000 , AR1
PORTW AR1 , DMSB
NOP
NOP
NOP
NOP
;set Division LSB
STM #TL_LCR , AR1
PORTW AR1 , LCR
NOP
NOP
NOP
NOP
;LCR init
;B loop
RSBX INTM
end: BD end
NOP
NOP
UART_INT:
PORTR IIR , AR1
ANDM #0x000F , AR1 ;obtain the A[3..0]
;CASE A[3..0]=0110b Line Status interrupt
;CASE =0100b Data available interrupt
;CASE =1100b time_out interrupt (FIF0 MODE)
;CASE =0010b transmitter holding register empty interrupt
;CASE =0000b Modem status interrupt
CMPM AR1 , #0x0006
CC Line_Status_int , TC
NOP
NOP
CMPM AR1 , #0x0004
CC Data_available_int , TC
NOP
NOP
CMPM AR1 , #0x000C
CC time_out_int , TC
NOP
NOP
CMPM AR1 , #0x0002
CC trans_hold_register_empty , TC
NOP
NOP
CMPM AR1 , #0x0000
CC Modem_status_int , TC
NOP
NOP
NOP
BD done ;default
NOP
NOP
Line_Status_int:
PORTR LSR , AR2
BD done
NOP
NOP
Data_available_int:
PORTR RBR , AR2
BD done
NOP
NOP
time_out_int:
PORTR RBR , AR2
BD done
NOP
NOP
trans_hold_register_empty:
STM #0x00AA , AR0
PORTW AR0 , THR
BD done
NOP
NOP
Modem_status_int:
PORTR MSR , AR2
BD done
NOP
NOP
done:
RSBX TC ; TC=0
RETE
NOP
NOP
.end
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