📄 top.rpt
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Project Information d:\aa\cpld\top.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 08/26/2007 19:43:25
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
top EPM7064SLC44-10 6 3 8 48 0 75 %
User Pins: 6 3 8
Project Information d:\aa\cpld\top.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
top@43 ALE
top@1 A15
top@31 FX
top@28 Gate
top@40 Lcd1
top@16 Lcd2
top@17 P00
top@18 P01
top@19 P02
top@20 P03
top@21 P04
top@24 P05
top@25 P06
top@26 P07
top@27 P10
top@29 P11
top@44 RD
Project Information d:\aa\cpld\top.rpt
** FILE HIERARCHY **
|frequency:19|
|frequency:19|bus8:8|
|frequency:19|bus8:8|lpm_bustri:lpm_bustri_component|
|frequency:19|bus8:7|
|frequency:19|bus8:7|lpm_bustri:lpm_bustri_component|
|frequency:19|bus8:6|
|frequency:19|bus8:6|lpm_bustri:lpm_bustri_component|
|frequency:19|bus8:5|
|frequency:19|bus8:5|lpm_bustri:lpm_bustri_component|
|frequency:19|counter32:35|
|frequency:19|counter32:35|lpm_counter:lpm_counter_component|
|mcu_ctrl:27|
|mcu_ctrl:27|74373:112|
|mcu_ctrl:27|74154:116|
Device-Specific Information: d:\aa\cpld\top.rpt
top
***** Logic for device 'top' compiled without errors.
Device: EPM7064SLC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R R R R
E E E E
S S S S
E E E E
R R R R L
V V V V G A A G V c
E E E C N 1 R L N E d
D D D C D 5 D E D D 1
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
RESERVED | 8 38 | #TDO
RESERVED | 9 37 | RESERVED
GND | 10 36 | RESERVED
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7064SLC44-10 34 | RESERVED
#TMS | 13 33 | RESERVED
RESERVED | 14 32 | #TCK
VCC | 15 31 | FX
Lcd2 | 16 30 | GND
P00 | 17 29 | P11
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
P P P P G V P P P P G
0 0 0 0 N C 0 0 0 1 a
1 2 3 4 D C 5 6 7 0 t
e
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\aa\cpld\top.rpt
top
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 14/16( 87%) 1/ 8( 12%) 0/16( 0%) 34/36( 94%)
B: LC17 - LC32 14/16( 87%) 7/ 8( 87%) 0/16( 0%) 35/36( 97%)
C: LC33 - LC48 13/16( 81%) 8/ 8(100%) 0/16( 0%) 28/36( 77%)
D: LC49 - LC64 7/16( 43%) 2/ 8( 25%) 0/16( 0%) 14/36( 38%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 18/32 ( 56%)
Total logic cells used: 48/64 ( 75%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 48/64 ( 75%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 15.41
Total fan-in: 740
Total input pins required: 6
Total fast input logic cells required: 0
Total output pins required: 3
Total bidirectional pins required: 8
Total reserved pins required 4
Total logic cells required: 48
Total flipflops required: 33
Total product terms required: 145
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 1/ 64 ( 1%)
Device-Specific Information: d:\aa\cpld\top.rpt
top
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT 0 0 0 0 0 0 4 ALE
1 - - INPUT 0 0 0 0 0 10 1 A15
31 (46) (C) INPUT 0 0 0 0 0 1 32 FX
17 24 B BIDIR 0 0 0 2 8 0 1 P00
18 21 B BIDIR 0 0 0 2 8 0 1 P01
19 20 B BIDIR 0 0 0 2 8 0 1 P02
20 19 B BIDIR 0 0 0 2 8 0 1 P03
21 17 B BIDIR 0 0 0 2 8 0 0 P04
24 33 C BIDIR 0 0 0 2 8 0 0 P05
25 35 C BIDIR 0 0 0 2 8 0 0 P06
26 36 C BIDIR 0 0 0 2 8 0 0 P07
27 (37) (C) INPUT 0 0 0 0 0 1 0 P10
29 (41) (C) INPUT 0 0 0 0 0 0 32 P11
44 - - INPUT 0 0 0 0 0 8 1 RD
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\aa\cpld\top.rpt
top
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
28 40 C FF t 0 0 0 2 0 0 32 Gate (|frequency:19|:1)
40 62 D OUTPUT t 0 0 0 1 4 0 0 Lcd1
16 25 B OUTPUT t 0 0 0 1 4 0 0 Lcd2
17 24 B TRI t 0 0 0 2 8 0 1 P00
18 21 B TRI t 0 0 0 2 8 0 1 P01
19 20 B TRI t 0 0 0 2 8 0 1 P02
20 19 B TRI t 0 0 0 2 8 0 1 P03
21 17 B TRI t 0 0 0 2 8 0 0 P04
24 33 C TRI t 0 0 0 2 8 0 0 P05
25 35 C TRI t 0 0 0 2 8 0 0 P06
26 36 C TRI t 0 0 0 2 8 0 0 P07
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
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