📄 top.rpt
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Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\fast_adc\top.rpt
top
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 29 B OUTPUT s t r 8 0 0 1 11 1 0 CK_out~fit~in1
- 9 A TFFE t 0 0 0 1 0 15 7 |div_clk:54|count0
- 6 A TFFE t 0 0 0 1 1 15 6 |div_clk:54|count1
- 10 A TFFE t 0 0 0 1 2 15 5 |div_clk:54|count2
- 18 B TFFE t 0 0 0 1 3 15 4 |div_clk:54|count3
- 12 A TFFE t 0 0 0 1 4 15 3 |div_clk:54|count4
(41) 64 D TFFE t 0 0 0 1 5 15 2 |div_clk:54|count5
- 60 D TFFE t 0 0 0 1 6 15 1 |div_clk:54|count6
- 22 B LCELL t 0 0 0 2 1 24 2 |mcu_ctrl:21|74373:112|:12
- 28 B LCELL t 0 0 0 2 1 24 2 |mcu_ctrl:21|74373:112|:13
- 27 B LCELL t 0 0 0 1 2 24 2 |mcu_ctrl:21|74373:112|:14
- 26 B LCELL t 0 0 0 1 2 24 2 |mcu_ctrl:21|74373:112|:15
(38) 56 D LCELL t 0 0 0 2 1 24 2 |mcu_ctrl:21|74373:112|:16
(16) 25 B SOFT s t 0 0 0 2 5 0 0 |74273b:18|Q8~1 (|74273b:18|~12~1)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\fast_adc\top.rpt
top
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------------- LC16 AD10
| +------------------- LC14 AD11
| | +----------------- LC11 AD12
| | | +--------------- LC5 AD13
| | | | +------------- LC4 AD14
| | | | | +----------- LC3 CK_out
| | | | | | +--------- LC9 |div_clk:54|count0
| | | | | | | +------- LC6 |div_clk:54|count1
| | | | | | | | +----- LC10 |div_clk:54|count2
| | | | | | | | | +--- LC12 |div_clk:54|count4
| | | | | | | | | | +- LC1 STATE_out
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC16 -> * * * * * - - - - - * | * - - - | <-- AD10
LC14 -> - * * * * - - - - - * | * - - - | <-- AD11
LC11 -> - - * * * - - - - - * | * - - - | <-- AD12
LC5 -> - - - * * - - - - - * | * - - - | <-- AD13
LC4 -> - - - - * - - - - - * | * - - - | <-- AD14
LC9 -> * * * * * - * * * * - | * * * * | <-- |div_clk:54|count0
LC6 -> * * * * * - - * * * - | * * * * | <-- |div_clk:54|count1
LC10 -> * * * * * - - - * * - | * * * * | <-- |div_clk:54|count2
LC12 -> * * * * * - - - - * - | * * * * | <-- |div_clk:54|count4
Pin
43 -> * * * * * - * * * * - | * * * * | <-- ALE
1 -> * * * * * - - - - - - | * * * * | <-- A15
44 -> * * * * * - - - - - - | * * * * | <-- RD
2 -> - - - - - - - - - - - | - * * - | <-- WR
LC37 -> * * * * * - - - - - * | * - * * | <-- AD0
LC40 -> * * * * * - - - - - * | * - * * | <-- AD1
LC41 -> * * * * * - - - - - * | * - * * | <-- AD2
LC46 -> * * * * * - - - - - * | * - - * | <-- AD3
LC51 -> * * * * * - - - - - * | * - - * | <-- AD4
LC49 -> * * * * * - - - - - * | * - - * | <-- AD5
LC52 -> * * * * * - - - - - * | * - - * | <-- AD6
LC53 -> * * * * * - - - - - * | * - - * | <-- AD7
LC57 -> * * * * * - - - - - * | * - - * | <-- AD8
LC62 -> * * * * * - - - - - * | * - - - | <-- AD9
LC29 -> - - - - - * - - - - - | * - - - | <-- CK_out~fit~in1
LC18 -> * * * * * - - - - * - | * * * * | <-- |div_clk:54|count3
LC64 -> * * * * * - - - - - - | * * * * | <-- |div_clk:54|count5
LC60 -> * * * * * - - - - - - | * * * * | <-- |div_clk:54|count6
LC22 -> * * * * * - - - - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:12
LC28 -> * * * * * - - - - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:13
LC27 -> * * * * * - - - - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:14
LC26 -> * * * * * - - - - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:15
LC56 -> * * * * * - - - - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:16
LC24 -> * * * * * - - - - - - | * * * * | <-- P00
LC21 -> * * * * * - - - - - * | * - * * | <-- P01
LC17 -> * * * * * - - - - - - | * * * * | <-- P04
LC33 -> * * * * * - - - - - - | * * * * | <-- P05
LC35 -> * * * * * - - - - - - | * * * * | <-- P06
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\top.rpt
top
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC29 CK_out~fit~in1
| +----------------------- LC18 |div_clk:54|count3
| | +--------------------- LC22 |mcu_ctrl:21|74373:112|:12
| | | +------------------- LC28 |mcu_ctrl:21|74373:112|:13
| | | | +----------------- LC27 |mcu_ctrl:21|74373:112|:14
| | | | | +--------------- LC26 |mcu_ctrl:21|74373:112|:15
| | | | | | +------------- LC24 P00
| | | | | | | +----------- LC21 P01
| | | | | | | | +--------- LC20 P02
| | | | | | | | | +------- LC19 P03
| | | | | | | | | | +----- LC17 P04
| | | | | | | | | | | +--- LC30 RAM_RD
| | | | | | | | | | | | +- LC25 |74273b:18|Q8~1
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC18 -> * * - - - - - - - - - - - | * * * * | <-- |div_clk:54|count3
LC22 -> - - * - - - * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:12
LC28 -> - - - * - - * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:13
LC27 -> - - - - * - * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:14
LC26 -> - - - - - * * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:15
LC24 -> * - - - - - - - - - - - - | * * * * | <-- P00
LC20 -> - - - - * - - - * - - - - | - * - - | <-- P02
LC19 -> - - - - - * - - - * - - - | - * - - | <-- P03
LC17 -> * - - - - - - - - - - - - | * * * * | <-- P04
Pin
43 -> * * * * * * - - - - - - - | * * * * | <-- ALE
1 -> - - - - - - * * * * * * * | * * * * | <-- A15
17 -> - - * - - - * - - - - - - | - * - - | <-- P00
18 -> - - - * - - - * - - - - - | - * - - | <-- P01
21 -> - - - - - - - - - - * - - | - * - * | <-- P04
44 -> - - - - - - - - - - - * * | * * * * | <-- RD
2 -> - - - - - - * * * * * - - | - * * - | <-- WR
LC9 -> * * - - - - - - - - - - - | * * * * | <-- |div_clk:54|count0
LC6 -> * * - - - - - - - - - - - | * * * * | <-- |div_clk:54|count1
LC10 -> * * - - - - - - - - - - - | * * * * | <-- |div_clk:54|count2
LC12 -> * - - - - - - - - - - - - | * * * * | <-- |div_clk:54|count4
LC64 -> * - - - - - - - - - - - - | * * * * | <-- |div_clk:54|count5
LC60 -> * - - - - - - - - - - - - | * * * * | <-- |div_clk:54|count6
LC56 -> - - - - - - * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:16
LC33 -> * - - - - - - - - - - - - | * * * * | <-- P05
LC35 -> * - - - - - - - - - - - - | * * * * | <-- P06
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\top.rpt
top
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------- LC37 AD0
| +----------- LC40 AD1
| | +--------- LC41 AD2
| | | +------- LC46 AD3
| | | | +----- LC33 P05
| | | | | +--- LC35 P06
| | | | | | +- LC36 P07
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'C'
LC | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC37 -> * * * * - - - | * - * * | <-- AD0
LC40 -> - * * * - - - | * - * * | <-- AD1
LC41 -> - - * * - - - | * - * * | <-- AD2
LC33 -> * * * * - - - | * * * * | <-- P05
LC35 -> * * * * - - - | * * * * | <-- P06
LC36 -> - - - - - - * | - - * - | <-- P07
Pin
43 -> * * * * - - - | * * * * | <-- ALE
1 -> * * * * * * * | * * * * | <-- A15
24 -> - - - - * - - | - - * - | <-- P05
25 -> - - - - - * - | - - * - | <-- P06
44 -> * * * * - - - | * * * * | <-- RD
2 -> - - - - * * * | - * * - | <-- WR
LC9 -> * * * * - - - | * * * * | <-- |div_clk:54|count0
LC6 -> * * * * - - - | * * * * | <-- |div_clk:54|count1
LC10 -> * * * * - - - | * * * * | <-- |div_clk:54|count2
LC18 -> * * * * - - - | * * * * | <-- |div_clk:54|count3
LC12 -> * * * * - - - | * * * * | <-- |div_clk:54|count4
LC64 -> * * * * - - - | * * * * | <-- |div_clk:54|count5
LC60 -> * * * * - - - | * * * * | <-- |div_clk:54|count6
LC22 -> * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:12
LC28 -> * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:13
LC27 -> * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:14
LC26 -> * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:15
LC56 -> * * * * * * * | * * * * | <-- |mcu_ctrl:21|74373:112|:16
LC24 -> * * * * - - - | * * * * | <-- P00
LC21 -> * * * * - - - | * - * * | <-- P01
LC17 -> * * * * - - - | * * * * | <-- P04
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\fast_adc\top.rpt
top
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------------- LC51 AD4
| +--------------- LC49 AD5
| | +------------- LC52 AD6
| | | +----------- LC53 AD7
| | | | +--------- LC57 AD8
| | | | | +------- LC62 AD9
| | | | | | +----- LC64 |div_clk:54|count5
| | | | | | | +--- LC60 |div_clk:54|count6
| | | | | | | | +- LC56 |mcu_ctrl:21|74373:112|:16
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC51 -> * * * * * * - - - | * - - * | <-- AD4
LC49 -> - * * * * * - - - | * - - * | <-- AD5
LC52 -> - - * * * * - - - | * - - * | <-- AD6
LC53 -> - - - * * * - - - | * - - * | <-- AD7
LC57 -> - - - - * * - - - | * - - * | <-- AD8
LC64 -> * * * * * * * * - | * * * * | <-- |div_clk:54|count5
LC60 -> * * * * * * - * - | * * * * | <-- |div_clk:54|count6
LC56 -> * * * * * * - - * | * * * * | <-- |mcu_ctrl:21|74373:112|:16
Pin
43 -> * * * * * * * * * | * * * * | <-- ALE
1 -> * * * * * * - - - | * * * * | <-- A15
21 -> - - - - - - - - * | - * - * | <-- P04
44 -> * * * * * * - - - | * * * * | <-- RD
2 -> - - - - - - - - - | - * * - | <-- WR
LC37 -> * * * * * * - - - | * - * * | <-- AD0
LC40 -> * * * * * * - - - | * - * * | <-- AD1
LC41 -> * * * * * * - - - | * - * * | <-- AD2
LC46 -> * * * * * * - - - | * - - * | <-- AD3
LC9 -> * * * * * * * * - | * * * * | <-- |div_clk:54|count0
LC6 -> * * * * * * * * - | * * * * | <-- |div_clk:54|count1
LC10 -> * * * * * * * * - | * * * * | <-- |div_clk:54|count2
LC18 -> * * * * * * * * - | * * * * | <-- |div_clk:54|count3
LC12 -> * * * * * * * * - | * * * * | <-- |div_clk:54|count4
LC22 -> * * * * * * - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:12
LC28 -> * * * * * * - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:13
LC27 -> * * * * * * - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:14
LC26 -> * * * * * * - - - | * * * * | <-- |mcu_ctrl:21|74373:112|:15
LC24 -> * * * * * * - - - | * * * * | <-- P00
LC21 -> * * * * * * - - - | * - * * | <-- P01
LC17 -> * * * * * * - - - | * * * * | <-- P04
LC33 -> * * * * * * - - - | * * * * | <-- P05
LC35 -> * * * * * * - - - | * * * * | <-- P06
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