c513.txt

dsp&c51的编程,从小百合上down的

发信人: reflection (似水流年), 信区: EEtechnology 
标  题: C51 Primer (2) Keil C51 Basics 
发信站: 南京大学小百合站 (Wed Nov 24 09:48:49 1999), 转信 
  
  
2 Keil C51 Compiler Basics - The 8051 Architecture 
The Keil C51 compiler has been written to allow C programmers to get code ru 
nning quickly on 8051 systems with little or no learning curve. However, to 
get the best from it, some appreciation of the underlying hardware is desira 
ble. The most basic decision to be made is which memory model to use. 
For general information on the C language, number and string representation, 
 please refer to a standard C textbook such as K & R 
2.1 8051 Memory Configurations 
2.1.1 Physical Location Of The Memory Spaces 
Perhaps the most initially confusing thing about the 8051 is that there are 
three different memory spaces, all of which start at the same address. 
Other microcontrollers, such as the 68HC11, have a single Von Neuman memory 
configuration, where memory areas are located at sequential addresses, regar 
dless of in what device they physically exist. 
Within the CPU there is one such, the DATA on-chip RAM. This starts at D:00 
(the 'D:' prefix implies DATA segment) and ends at 07fH (127 decimal). This 
RAM can be used for program variables. It is directly addressable, so that i 
nstructions like 'MOV A,x' are usable. Above 80H the special function regist 
ers are located, which are again directly addressable. However, a second mem 
ory area exists between 80H and 0FFH which is only indirectly addressable an 
d is prefixed by I: and known as IDATA. It is only accessible via indirect a 
ddressing (MOV A,@Ri) and effectively overlays the directly addressable sfr 
area. This constitutes an extended on-chip RAM area and was added to the ord 
inary 8051 design when the 8052 appeared. As it is only indirectly addressab 
le, it is best left for stack use, which is, by definition, always indirectl 
y addressed via the stack pointer SP. Just to confuse things, the normal dir 
ectly addressable RAM from 0-80H can also be indirectly addressed by the MOV 
 A,@Ri instruction! 
Fig.1. - The 8051's Memory Spaces. 
A third memory space, the CODE segment, also starts at zero, but this is res 
erved for the program. It typically runs from C:0000 to C:0FFFFH (65536 byte 
s) but as it is held within an external EPROM, it can be any size up to 64KB 
 (65536 bytes). The CODE segment is accessed via the program counter (PC) fo 
r opcode fetches and by DPTR for data. Obviously, being ROM, only constants 
can be stored here. 
A fourth memory area is also off-chip, starting at X:0000. This exists in an 
 external RAM device and, like the C:0000 segment, can extend up to X:0FFFFH 
 (65536 bytes). The 'X:' prefix implies the external XDATA segment. The 8051 
's only 16 bit register, the DPTR (data pointer) is used to access the XDATA 
. Finally, 256 bytes of XDATA can also be addressed in a paged mode. Here an 
 8 bit register (R0) is used to access this area, termed PDATA. 
The obvious question is: "How does the 8051 prevent an access to C:0000 resu 
lting in data being fetched from D:00?" 
The answer is in the 8051 hardware: When the cpu intends to access D:00, the 
 on-chip RAM is enabled by a purely internal READ signal - the external /RD 
pin is unchanged. 
    MOV   A,40      ; Put value held in location 40 into the accumulator. 
                      This addressing mode (direct) is the basis of the 
                      SMALL memory model. 
    MOV   R0,#0A0H  ; Put the value held in IDATA location 0A0H into 
    MOV   A,@R0     ; the accumulator 
This addressing mode is used to access the indirectly addressable on-chip me 
mory above 80H and as an alternative way to get at the direct memory below t 
his address. 
A variation on DATA is BDATA (bit data). This is a 16 byte (128 bit) area, s 
tarting at 020H in the direct segment. It is useful in that it can be both a 
ccessed byte-wise by the normal MOV instructions and addressed by special bi 
t-orientated intructions, as shown below: 
    SETB  20.0  ; 
    CLRB  20.0  ; 
The external EPROM device (C:0000) is not enabled during RAM access. In fact 
, the external EPROM is only enabled when a pin on the 8051 named the PSEN ( 
program store enable) is pulled low. The name indicates that the main functi 
on of the EPROM is to hold the program. 
The XDATA RAM and CODE EPROM do not clash as the XDATA device is only active 
 during a request from the 8051 pins named READ or WRITE, whereas the CODE d 
evice only responds when the PSEN pin is low. 
To help access the external XDATA RAM, special instructions exist, convenien 
tly containing an 'X'.... 
MOV   DPTR,#08000H 
MOVX  A,@DPTR       ; "Put a value in A located at address in the 
                       external RAM, contained in the DPTR register (8000H)" 
. 
The above addressing mode forms the basis of the LARGE model. 
    MOVX  R0,#080H  ; 
    MOVX  A,@R0     ; 
This alternative access mode to external RAM forms the basis of the COMPACT 
memory model. Note that if Port 2 is attached to the upper address lines of 
the RAM, it can act like a manually operated "paging" control. 
The important point to remember is that the PSEN pin is active when instruct 
ions are being fetched; READ and WRITE are active when MOVX.... ("move exter 
nal") instructions are being carried-out. 
Note that the 'X' means that the address is not within the 8051 but is conta 
ined in an external device, enabled by the READ and WRITE pins. 
2.1.2 Possible Memory Models 
With a microcontroller like the 8051, the first decision is which memory mod 
el to use. Whereas the PC programmer chooses between TINY, SMALL, MEDIUM, CO 
MPACT, LARGE and HUGE to control how the processor segmentation of the RAM i 
s to be used (overcome!), the 8051 user has to decide where the program and 
data are to reside. 
C51 currently supports the following memory configurations: 
ROM: currently the largest single object file that can be produced is 64K, a 
lthough up to 1MB can be supported with the BANKED model described below. Al 
l compiler output to be directed to Eprom/ROM, constants, look-up tables etc 
., should be declared as "code". 
RAM: There are three memory models, SMALL, COMPACT and LARGE 
SMALL: all variables and parameter-passing segments will be placed in the 80 
51's internal memory. 
COMPACT: variables are stored in paged memory addressed by ports 0 and 2. In 
direct addressing opcodes are used. On-chip registers are still used for loc 
als and parameters. 
LARGE: variables etc. are placed in external memory addressed by @DPTR. On-c 
hip registers are still used for locals and parameters. 
BANKED: Code can occupy up to 1MB by using either CPU port pins or memory-ma 
pped latches to page memory above 0xFFFF. Within each 64KB memory block a CO 
MMON area must be set aside for C library code. Inter-bank function calls ar 
e possible. 
See the section on BL51 for more information on the BANKED model. 
A variation on these models is to use one model globally and then to force c 
ertain variables and data objects into other memory spaces. 
This technique is covered later. 
2.1.3 Choosing The Best Memory Configuration/Model 
With the four memory models, a decision has to be made as to which one to us 
e. Single chip 8051 users may only use the SMALL model, unless they have an 
external RAM fitted which can be page addressed from Port 0 and optionally, 
Port 2, using MOVX A,@R0 addressing. 
This permits the COMPACT model. While it is possible to change the global me 
mory model half way through a project, it is not recommended! 
SMALL: Total RAM 128 bytes (8051/31) 
Rather restricting in the case of 8051/31. Will support code sizes up to abo 
ut 4K but a constant check must be kept on stack usage. The number of global 
 variables must be kept to a minimum to allow the linker OVERLAYer to work t 
o best effect. With 8052/32 versions, the manual use of the 128 byte IDATA a 
rea above 80H can allow applications up to about 10-12K but again the stack 
position must be kept in mind. 
Very large programs can be supported by the SMALL model by manually forcing 
large and/or slow data objects in to an external RAM, if fitted. Also variab 
les which need to be viewed in real time are best located here, as dual-port