ctr_tdi.srr

本程序RS232通信的一个实验小程序,其中还有rs232和rs485的介绍!

$ Start of Compile
#Sun Apr 25 14:01:50 2004

Synplicity VHDL Compiler, version Compilers 7.3, Build 073R, built May 30 2003
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

@N:"G:\My_Designs\jtest\jtag0\src\ctr_tdi.vhd":59:7:59:18|Top entity is set to ctr_tdi_able.
VHDL syntax check successful!
Synthesizing work.ctr_tdi_able.ctr_tdi
Post processing for work.ctr_tdi_able.ctr_tdi
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Xilinx Technology Mapper, version 7.3, Build 170R, built Jun  6 2003
Copyright (C) 1994-2003, Synplicity Inc.  All Rights Reserved


Automatic dissolve during optimization of view:work.ctr_tdi_able(ctr_tdi) of un6_m_1(PM_ADDC__0_4)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base G:\Program Files\synplicity\Synplify_73\examples\rev_3\ctr_tdi.srm
Writing EDIF Netlist and constraint files
@N|Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
Resource Usage Report for ctr_tdi_able 

Mapping to part: xc95144pq100-7
Simple gate primitives:
AND2            14 uses
AND2B1          3 uses
FD              4 uses
OR2             6 uses
XOR2            2 uses

I/O primitives:
IBUF           5 uses
OBUF           1 use

BUFG           1 use

I/O Register bits:                  0
Register bits not including I/Os:   4

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
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