jtagtest.srr

本程序RS232通信的一个实验小程序,其中还有rs232和rs485的介绍!

$ Start of Compile
#Sun Apr 25 14:50:43 2004

Synplicity VHDL Compiler, version Compilers 7.3, Build 073R, built May 30 2003
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
File G:\My_Designs\jtest\jtag0\src\sel_full_in_out_tms.vhd changed - recompiling
Synthesizing work.jtag.jtag
Synthesizing work.datashift_and_out.behav
Post processing for work.datashift_and_out.behav
Synthesizing work.datashift.behav
Post processing for work.datashift.behav
Synthesizing work.input_data.behav
Post processing for work.input_data.behav
Synthesizing work.zhiwei3.zhiwei3
Post processing for work.zhiwei3.zhiwei3
Synthesizing work.sel_out.behav
Post processing for work.sel_out.behav
Synthesizing work.cmd_enable.cmd_enable
Post processing for work.cmd_enable.cmd_enable
Synthesizing work.cmd_tms.cmd_tms
Post processing for work.cmd_tms.cmd_tms
Synthesizing work.cmd_in.behav
Post processing for work.cmd_in.behav
Synthesizing work.ctr_tdi_able.ctr_tdi
Post processing for work.ctr_tdi_able.ctr_tdi
Synthesizing work.ctr_shift.ctr_shift
Post processing for work.ctr_shift.ctr_shift
Synthesizing work.ctr.behav
Post processing for work.ctr.behav
Synthesizing work.tdi3_ena.tdi3_ena
Post processing for work.tdi3_ena.tdi3_ena
Synthesizing work.sel_out_in.sel
Post processing for work.sel_out_in.sel
Synthesizing work.sel_in_shift.behav
Post processing for work.sel_in_shift.behav
Synthesizing work.data_in_tms.data_in_tms
Post processing for work.data_in_tms.data_in_tms
Synthesizing work.cmd_select.cmd_select
Post processing for work.cmd_select.cmd_select
Post processing for work.jtag.jtag
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Xilinx Technology Mapper, version 7.3, Build 170R, built Jun  6 2003
Copyright (C) 1994-2003, Synplicity Inc.  All Rights Reserved


Automatic dissolve at startup in view:work.jtag(jtag) of U7(input_data)
Automatic dissolve at startup in view:work.jtag(jtag) of U2(cmd_in)
Automatic dissolve during optimization of view:work.tdi3_ena(tdi3_ena) of un6_m_1(PM_ADDC__0_6)
Automatic dissolve during optimization of view:work.ctr_tdi_able(ctr_tdi) of un6_m_1(PM_ADDC__0_4)
Automatic dissolve during optimization of view:work.cmd_enable(cmd_enable) of un13_m_1(PM_ADDC__0_4)
Automatic dissolve during optimization of view:work.zhiwei3(zhiwei3) of un13_m_1(PM_ADDC__0_6)
Automatic dissolve during optimization of view:work.datashift(behav) of un6_m_1(PM_ADDC__0_6)

Clock Buffers:
  Inserting Clock buffer for port tck,	TNM=tck

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base G:\Program Files\synplicity\Synplify_73\examples\rev_3\jtagtest.srm
Writing EDIF Netlist and constraint files
@N|Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
Resource Usage Report for jtag 

Mapping to part: xc95144pq100-7
Simple gate primitives:
AND2            526 uses
AND2B1          330 uses
FD              237 uses
FDC             22 uses
FDP             1 use
OR2             361 uses
XOR2            19 uses

I/O primitives:
IBUF           13 uses
OBUF           1 use
OBUFT          1 use

BUFG           1 use

I/O Register bits:                  0
Register bits not including I/Os:   260

Internal tri-state buffer usage summary
TBUFs + BUFEs: 2

Mapper successful!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
###########################################################]