cmd_shift_enable.srr

本程序RS232通信的一个实验小程序,其中还有rs232和rs485的介绍!

$ Start of Compile
#Sat Apr 24 20:47:18 2004

Synplicity VHDL Compiler, version Compilers 7.3, Build 073R, built May 30 2003
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

@N:"G:\My_Designs\jtest\jtag0\src\cmd_shift_enable.vhd":53:7:53:10|Top entity is set to jtag.
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

Synthesizing work.jtag.jtag
Post processing for work.jtag.jtag
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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Synplicity Xilinx Technology Mapper, version 7.3, Build 170R, built Jun  6 2003
Copyright (C) 1994-2003, Synplicity Inc.  All Rights Reserved


Automatic dissolve during optimization of view:work.jtag(jtag) of un13_m_1(PM_ADDC__0_4)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base G:\Program Files\synplicity\Synplify_73\examples\rev_3\cmd_shift_enable.srm
Writing EDIF Netlist and constraint files
@N|Timing Report not generated for this device, please use place and route tools for timing analysis.
---------------------------------------
Resource Usage Report for jtag 

Mapping to part: xc95144pq100-7
Simple gate primitives:
AND2            8 uses
FDC             4 uses
OR2             4 uses
XOR2            1 use

I/O primitives:
IBUF           1 use
OBUF           1 use

BUFG           1 use

I/O Register bits:                  0
Register bits not including I/Os:   4

Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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