📄 ave2kregs.h
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#ifndef _AVE2KREGS_H
#define _AVE2KREGS_H
/*
#define I2C_TRANSFER 0x8c
#define I2C_STATUS 0x90
#define GPIO_CTRL 0xe0
#define AUDIO_CFG1 0xf4
#define AUDIO_CFG2 0xf8
#define MC1 0xfc
#define MC2 0x100
*/
#define GP3_HIGH 0x50000000
#define GP3_LOW 0x40000000
#define GP2_HIGH 0x00500000
#define GP2_LOW 0x00400000
#define GP1_HIGH 0x00005000
#define GP1_LOW 0x00004000
#define GP0_HIGH 0x00000050
#define GP0_LOW 0x00000040
// Bit mask constants
#define MASK_00 0x00000001 // Mask value for bit 0
#define MASK_01 0x00000002 // Mask value for bit 1
#define MASK_02 0x00000004 // Mask value for bit 2
#define MASK_03 0x00000008 // Mask value for bit 3
#define MASK_04 0x00000010 // Mask value for bit 4
#define MASK_05 0x00000020 // Mask value for bit 5
#define MASK_06 0x00000040 // Mask value for bit 6
#define MASK_07 0x00000080 // Mask value for bit 7
#define MASK_08 0x00000100 // Mask value for bit 8
#define MASK_09 0x00000200 // Mask value for bit 9
#define MASK_10 0x00000400 // Mask value for bit 10
#define MASK_11 0x00000800 // Mask value for bit 11
#define MASK_12 0x00001000 // Mask value for bit 12
#define MASK_13 0x00002000 // Mask value for bit 13
#define MASK_14 0x00004000 // Mask value for bit 14
#define MASK_15 0x00008000 // Mask value for bit 15
#define MASK_16 0x00010000 // Mask value for bit 16
#define MASK_17 0x00020000 // Mask value for bit 17
#define MASK_18 0x00040000 // Mask value for bit 18
#define MASK_19 0x00080000 // Mask value for bit 19
#define MASK_20 0x00100000 // Mask value for bit 20
#define MASK_21 0x00200000 // Mask value for bit 21
#define MASK_22 0x00400000 // Mask value for bit 22
#define MASK_23 0x00800000 // Mask value for bit 23
#define MASK_24 0x01000000 // Mask value for bit 24
#define MASK_25 0x02000000 // Mask value for bit 25
#define MASK_26 0x04000000 // Mask value for bit 26
#define MASK_27 0x08000000 // Mask value for bit 27
#define MASK_28 0x10000000 // Mask value for bit 28
#define MASK_29 0x20000000 // Mask value for bit 29
#define MASK_30 0x40000000 // Mask value for bit 30
#define MASK_31 0x80000000 // Mask value for bit 31
#define MASK_B0 0x000000ff // Mask value for byte 0
#define MASK_B1 0x0000ff00 // Mask value for byte 1
#define MASK_B2 0x00ff0000 // Mask value for byte 2
#define MASK_B3 0xff000000 // Mask value for byte 3
#define MASK_W0 0x0000ffff // Mask value for word 0
#define MASK_W1 0xffff0000 // Mask value for word 1
#define MASK_PA 0xfffffffc // Mask value for physical address
#define MASK_PR 0xfffffffe // Mask value for protection register
#define MASK_ER 0xffffffff // Mask value for the entrie register
#define MASK_NONE 0x00000000 // No mask
//MC1 bits
#define EI2C 0x0100
#define TR_E_1 0x40
#define TR_E_2 0x20
#define TR_E_3 0x10
#define EVP 0x400
//MC2 bits
#define UPLD_HPS_V 0x0020
#define UPLD_DMA3 0x0010
#define UPLD_DMA2 0x0008
#define UPLD_DMA1 0x0004
#define UPLD_DEBI 0x0002
#define UPLD_IIC 0x0001
enum SpciReg {
//---------- Start of register structure
BASE_ODD1 = 0x00, // Video DMA 1 registers
BASE_EVEN1 = 0x04,
PROT_ADDR1 = 0x08,
PITCH1 = 0x0C,
BASE_PAGE1 = 0x10, // Video DMA 1 base page
NUM_LINE_BYTE1 = 0x14,
BASE_ODD2 = 0x18, // Video DMA 2 registers
BASE_EVEN2 = 0x1C,
PROT_ADDR2 = 0x20,
PITCH2 = 0x24,
BASE_PAGE2 = 0x28, // Video DMA 2 base page
NUM_LINE_BYTE2 = 0x2C,
BASE_ODD3 = 0x30, // Video DMA 3 registers
BASE_EVEN3 = 0x34,
PROT_ADDR3 = 0x38,
PITCH3 = 0x3C,
BASE_PAGE3 = 0x40, // Video DMA 3 base page
NUM_LINE_BYTE3 = 0x44,
//---------- // DMA Busts & FIFO Thresholds
PCI_BT_V1 = 0x48, // Video/FIFO 1
PCI_BT_V2 = 0x49, // Video/FIFO 2
PCI_BT_V3 = 0x4A, // Video/FIFO 3
PCI_BT_DEBI = 0x4B, // DEBI
PCI_BT_A = 0x4C, // Audio
//----------
DD1_INIT = 0x50, // Init setting of DD1 interface
//----------
DD1_STREAM_B = 0x54, // DD1 B video data stream handling
DD1_STREAM_A = 0x56, // DD1 A video data stream handling
//----------
BRS_CTRL = 0x58, // BRS control register
HPS_CTRL = 0x5C, // HPS control register
HPS_V_SCALE = 0x60, // HPS vertical scale
HPS_V_GAIN = 0x64, // HPS vertical ACL and gain
HPS_H_PRESCALE = 0x68, // HPS horizontal prescale
HPS_H_SCALE = 0x6C, // HPS horizontal scale
BCS_CTRL = 0x70, // BCS control
CHROMA_KEY_RANGE = 0x74,
CLIP_FORMAT_CTRL = 0x78, // HPS outputs, formats & clipping
//----------
DEBI_CONFIG = 0x7C,
DEBI_COMMAND = 0x80,
DEBI_PAGE = 0x84,
DEBI_AD = 0x88,
//----------
I2C_TRANSFER = 0x8C,
I2C_STATUS = 0x90,
//----------
BASE_A1_IN = 0x94, // Audio 1 input DMA
PROT_A1_IN = 0x98,
PAGE_A1_IN = 0x9C,
BASE_A1_OUT = 0xA0, // Audio 1 output DMA
PROT_A1_OUT = 0xA4,
PAGE_A1_OUT = 0xA8,
BASE_A2_IN = 0xAC, // Audio 2 input DMA
PROT_A2_IN = 0xB0,
PAGE_A2_IN = 0xB4,
BASE_A2_OUT = 0xB8, // Audio 2 output DMA
PROT_A2_OUT = 0xBC,
PAGE_A2_OUT = 0xC0,
//----------
RPS_PAGE0 = 0xC4, // RPS task 0 page register
RPS_PAGE1 = 0xC8, // RPS task 1 page register
//----------
RPS_THRESH0 = 0xCC, // HBI threshold for task 0
RPS_THRESH1 = 0xD0, // HBI threshold for task 1
RPS_TOV0 = 0xD4, // RPS timeout for task 0
RPS_TOV1 = 0xD8, // RPS timeout for task 1
//----------
IER = 0xDC, // Interrupt enable register
//----------
GPIO_CTRL = 0xE0, // GPIO 0-3 register
//----------
EC1SSR = 0xE4, // Event cnt set 1 source select
EC2SSR = 0xE8, // Event cnt set 2 source select
ECT1R = 0xEC, // Event cnt set 1 thresholds
ECT2R = 0xF0, // Event cnt set 2 thresholds
//----------
ACON1 = 0xF4,
ACON2 = 0xF8,
//----------
MC1 = 0xFC, // Main control register 1
MC2 = 0x100, // Main control register 2
//----------
RPS_ADDR0 = 0x104, // RPS task 0 address register
RPS_ADDR1 = 0x108, // RPS task 1 address register
//----------
ISR = 0x10C, // Interrupt status register
PSR = 0x110, // Primary status register
SSR = 0x114, // Secondary status register
//----------
EC1R = 0x118, // Event counter set 1 register
EC2R = 0x11C, // Event counter set 2 register
//----------
PCI_VDP1 = 0x120, // Video DMA pointer of FIFO 1
PCI_VDP2 = 0x124, // Video DMA pointer of FIFO 2
PCI_VDP3 = 0x128, // Video DMA pointer of FIFO 3
PCI_ADP1 = 0x12C, // Audio DMA pointer of audio out 1
PCI_ADP2 = 0x130, // Audio DMA pointer of audio in 1
PCI_ADP3 = 0x134, // Audio DMA pointer of audio out 2
PCI_ADP4 = 0x138, // Audio DMA pointer of audio in 2
PCI_DMA_DDP = 0x13C, // DEBI DMA pointer
//----------
LEVEL_REP = 0x140, //Level_Report of Saa7146 in Ave2k
FEEDBACKBUF1 = 0x144,
A_TIME_SLOT1 = 0x180, // from 180 - 1BC
A_TIME_SLOT2 = 0x1C0, // from 1C0 - 1FC
//----------
END_OF_MEM_REG = 0x200 // invalid register offset
}; // end of SpciReg
//DEBI_CONFIG bits
#define DBC_XIRQEN 0x80000000
#define DBC_XRESUME 0x40000000
#define DBC_FAST 0x10000000
#define DBC_SWAP_NONE 0x00000000
#define DBC_SWAP_2 0x00100000
#define DBC_SWAP_4 0x00200000
#define DBC_SLAVE16 0x00080000
#define DBC_ADDINC 0x00040000
#define DBC_INTEL 0x00020000
#define DBC_TIEN 0x00000000
#define DBC_TIDS 0x00010000
//DEBI COMMAND bits
#define DEBI_WRITE 0x00000000
#define DEBI_READ 0x00010000
#define ENABLE_DEBI 0x08000800
//video output formats
#define RGB16 0x80
#define RGB24 0x81
#define RGB32 0x82
#define RGB1555 0x83
#define RGB5515 0x84
#define RGB8 0x87
#define YUV422 0x00
#define YUV2 0x04
#define Y8 0x06
#endif⌨️ 快捷键说明
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