📄 saa7114.c
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//************************************//
//File Name: SAA7114.cpp
//
//Contents:
// The interface to control video decoder
// SAA7114.Philips Semiconductors
//
// Set and get brightness,contrast,saturation and hue of video output
// SetVideoParameter
// GetVideoParameter
// SetVideoSource
// GetVideoType
// SetVideoGain
// GetVideoScale
// SetVideoScale
// SoftwareReset
//
// 23-Feb-2002,zhengchan,add:
// GetVideoScale
// SetVideoScale
//************************************//
//creation, Version history:
// zhengchan, 4-Feb-2002, 1.0.0
//************************************//
#include "AVE6K.h"
#include "Ave6kif.h"
#include "IIC.h"
#include "SAA7114.h"
#include "version.h"
#include "stdio.h"
struct IICReg {
unsigned char bySub;
unsigned char byData;
}Reg7114Default[]={
//Pefer to SAA7114H_1.pdf and mark the page at the end of definition.
//{0, 0x00}, //read only
//Video decoder: 01H to 2FH
{0x01 , 0x08}, //Horizontal increment delay; P89
{0x02 , 0xc4},//0xc2}, //0xc0}, //Analog input control 1 (AICO1);
{0x03 , 0x13}, //0x10}, //Analog input control 2 (AICO2); P92
{0x04 , 0xff}, //144}, //Analog input control 3 (AICO3):
{0x05 , 0xff}, //144}, //Analog input control 4 (AICO4);
{0x06 , 0xeb}, //Horizontal sync start; P93
{0x07 , 0xe0}, //Horizontal sync stop;
{0x08 , 0x98}, //0x8c}, //0x9c}, //0xbc}, //Sync control; P94
{0x09 , 0x40}, //Luminance control; P95
{0x0a , 0x80}, //Luminance brightness control: decoder part;
{0x0b , 0x44}, //Luminance contrast control; decoder part; P96
{0x0c , 0x40}, //Chrominance saturation control: decoder part;
{0x0d , 0x00}, //Chrominance hue control;
{0x0e , 0x01}, //Chrominance control 1; P97
{0x0f , 0x00}, //Chrominance gain control;
{0x10 , 0x00}, //Chrominance control 2; P98
{0x11 , 0x00}, //Mode/delay control;
{0x12 , 0xc9}, //0x00}, //0x8f}, //0xf8}, //0xd8}, //0xc7}, //RT signal control: RTS0[3:0]/PRS0[7:4] output; p99
{0x13 , 0x00}, //0x10}, //0x91}, //0x82}, //0x92}, //0x90}, //0x80}, //RT/X-port output control; p101
{0x14 , 0x00}, //Analog/ADC/compatibility control; p102
{0x15 , 0x15}, //0x00}, //VGATE pulse; FID polarity change; p103
{0x16 , 0x34}, //0x00}, //VGATE stop;
{0x17 , 0x02}, //0x00}, //Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0] p105
{0x18 , 0x40}, //Raw data gain control;
{0x19 , 0x80}, //Raw data offset control;
/* 0x1a - 0x1e, reserved*/
/* ...... */
{0x1f , 0x00}, //read only, Status byte video decoder; P106
/* 0x20 - 0x2f, reserved*/
/* ...... */
//Audio clock generation: 30H to 3FH
//AMCLK=256*32 kHZ=0x2000kHZ=8.192MHZ
{0x30 , 0x00}, //Audio master clock (AMCLK) cycles per field p106
{0x31 , 0x80}, //...
{0x32 , 0x02}, //... 0x30,0x31,0x32 --(FIELD:50HZ)ACPF= 0x28000HZ
{0x33 , 0x00}, //reserved
{0x34 , 0xab}, //Audio master clock (AMCLK) nominal increment p107
{0x35 , 0xaa}, //...
{0x36 , 0x2a}, //... 0x34,0x35,0x36 --(FIELD:50HZ)ACNI= 0x2aaaabHZ
{0x37 , 0x00}, // **** NO illuminate ****
{0x38 , 0x03}, //Clock ratio AMCLK (audio master clock) to ASCLK (serial bit clock)
{0x39 , 0x10}, //Clock ratio ASCLK (serial bit clock) to ALRCLK (channel select clock)
{0x3a , 0x00}, //Audio clock control;
/* 0x3b - 0x3f, reserved */
/* ...... */
//General purpose VBI-data slicer: 40H to 7FH
{0x40 , 0x00}, //Slicer control 1; p107
{0x41 , 0xff}, //Line control register; P108
{0x42 , 0xff}, //...
{0x44 , 0xff}, //...
{0x45 , 0xff}, //...
{0x46 , 0xff}, //...
{0x47 , 0xff}, //...
{0x48 , 0xff}, //...
{0x49 , 0xff}, //...
{0x4a , 0xff}, //...
{0x4b , 0xff}, //...
{0x4c , 0xff}, //...
{0x4d , 0xff}, //...
{0x4e , 0xff}, //...
{0x4f , 0xff}, //...
{0x50 , 0xff}, //...
{0x51 , 0xff}, //...
{0x52 , 0xff}, //...
{0x53 , 0xff}, //...
{0x54 , 0xff}, //...
{0x55 , 0xff}, //...
{0x56 , 0xff}, //...
{0x57 , 0xff}, //...
{0x58 , 0x40}, //Programmable framing code; P108
{0x59 , 0x47}, //Horizontal offset for slicer; slicer set 59H and 5BH
{0x5a , 0x03}, //Vertical offset for slicer; P109
{0x5b , 0x03}, //Field offset, and MSBs for horizontal and vertical offsets;
{0x5c , 0x00}, // **** NO illuminate ****
{0x5d , 0x00}, //Header and data identification (DID; ITU 656) code control;
{0x5e , 0x00}, //Sliced data identification (SDID) code;
{0x5f , 0x00}, // **** NO illuminate ****
{0x60 , 0x00}, //read only, Slicer status byte 0; P110
{0x61 , 0x00}, //read only, Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]
{0x62 , 0x00}, //read only
{0x63 , 0x00}, // **** NO illuminate ****
/* 0x64 - 0x7f, reserved*/
/* ...... */
//X-port, I-port and the scaler: 80H to EFH
{0x80 , 0x10}, //0x30}, //0x10}, //0x12}, //Global control 1; P110
{0x81 , 0x00}, // **** NO illuminate ****
{0x82 , 0x00}, // **** NO illuminate ****
{0x83 , 0x02}, //X-port I/O enable and output clock phase control; P110 - P115
{0x84 , 0xf4},//0xf0}, //I-port output signal definitions;
{0x85 , 0x00},//0x00}, //I-port reference signal polarities;
{0x86 , 0x45},//0x4f}, //I-port FIFO flag control and arbitration;
{0x87 , 0x01}, //0x02}, //port I/O enable, output clock and gated clock phase control;
{0x88 , 0xf0}, //0x01}, //Power save control; P115
{0x89 , 0x00}, // **** NO illuminate ****
{0x8a , 0x00}, // **** NO illuminate ****
{0x8b , 0x00}, // **** NO illuminate ****
{0x8c , 0x00}, // **** NO illuminate ****
{0x8d , 0x00}, // **** NO illuminate ****
{0x8e , 0x00}, // **** NO illuminate ****
{0x8f , 0x00}, //read only,Status information scaler part; P116
{0x90 , 0x04},//0x01},//0x06},//0x04}, //Task handling control; P117
{0x91 , 0x08},//0x08},//0x30}, //16-bit;X-port formats and configuration; P118
{0x92 , 0x10}, //X-port input reference signal definitions; P119
{0x93 , 0x0a},//0x88},//0x0a},//0x4a},//0x42},//0xc2}, //4:2:0; Dwords are transferred 16-bit word(93H[6]=1) or byte(93H[6]=0) wise;I-port output format and configuration; P120
{0x94 , 0x0a}, //Horizontal input window start; P121
{0x95 , 0x00}, //... (XO) 94H,95H = 16
{0x96 , 0xd0},//0xc0}, //Horizontal input window length;
{0x97 , 0x02}, //... (XS) 输入图象大小，720*576; 720=0x02d0
{0x98 , 0x14}, //Vertical input window start;
{0x99 , 0x00}, //... (YO) 98H,99H = 10
{0x9a , 0x22}, //Vertical input window length; 576/2 = 288;
{0x9b , 0x01}, //... (YS) 9aH,9bH = 0x0120+2 Decimal: 576/2+2;
{0x9c , 0x60},//0xc0}, //Horizontal output window length; P122
{0x9d , 0x01},//0x02}, //... (XD) 输出图象大小是:352*288; 352=0x0160
{0x9e , 0x20}, //Vertical output window length;
{0x9f , 0x01}, //... (YD) 288=0x0120
//0xa0 - 0xa7: Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H)
//0xa8 - 0xaf: Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH)
{0xa0 , 0x02},//0x01}, //Horizontal prescaling; P123
{0xa1 , 0x02},//0x00}, //?? Accumulation length;
{0xa2 , 0xaa},//0x00}, //?? Prescaler DC gain and FIR prefilter control;
{0xa3 , 0x00}, // **** NO illuminate ****
{0xa4 , 0x80},//0xa0}, //128;Luminance brightness setting; P124
{0xa5 , 0x40}, //64; Luminance contrast setting;
{0xa6 , 0x40}, //64; Chrominance saturation setting;
{0xa7 , 0x00}, // **** NO illuminate ****
{0xa8 , 0x18},//0x00},//0x5d},//0x18}, //Horizontal luminance scaling increment; P125
{0xa9 , 0x04}, //fisc*1024 = 1048 =0x0418
{0xaa , 0x00}, //Horizontal luminance phase offset;
{0xab , 0x00},
{0xac , 0x0c},//0x2e}, //Horizontal chrominance scaling increment;
{0xad , 0x02}, //524=0x020c; =1/2的Horizontal luminance scaling increment[A8,A9]
{0xae , 0x00}, //Horizontal chrominance phase offset;
{0xaf , 0x00},
{0xb0 , 0x00}, //Vertical luminance scaling increment; P126
{0xb1 , 0x04}, //vsc*1024 =2048 = 0x0800
{0xb2 , 0x00}, //Vertical chrominance scaling increment;
{0xb3 , 0x04}, //... 等于 [b0H,b1H]
{0xb4 , 0x00},//0x01}, //??Vertical scaling mode control;
{0xb5 , 0x00},
{0xb6 , 0x00},
{0xb7 , 0x00},
{0xb8 , 0x00}, //Vertical chrominance phase offset ‘00’;
{0xb9 , 0x00},
{0xba , 0x00},
{0xbb , 0x00},
{0xbc , 0x00}, //Vertical luminance phase offset ‘00’; P127
{0xbd , 0x00},
{0xbf , 0x00}
};
struct IICReg Reg7114Back[]={
//Pefer to SAA7114H_1.pdf and mark the page at the end of definition.
//{0, 0x00}, //read only
//Video decoder: 01H to 2FH
{0x01 , 0x08}, //Horizontal increment delay; P89
{0x02 , 0xc4},//0xc2}, //0xc0}, //Analog input control 1 (AICO1);
{0x03 , 0x13}, //0x10}, //Analog input control 2 (AICO2); P92
{0x04 , 0xff}, //144}, //Analog input control 3 (AICO3):
{0x05 , 0xff}, //144}, //Analog input control 4 (AICO4);
{0x06 , 0xeb}, //Horizontal sync start; P93
{0x07 , 0xe0}, //Horizontal sync stop;
{0x08 , 0x98}, //0x8c}, //0x9c}, //0xbc}, //Sync control; P94
{0x09 , 0x40}, //Luminance control; P95
{0x0a , 0x80}, //Luminance brightness control: decoder part;
{0x0b , 0x44}, //Luminance contrast control; decoder part; P96
{0x0c , 0x40}, //Chrominance saturation control: decoder part;
{0x0d , 0x00}, //Chrominance hue control;
{0x0e , 0x01}, //Chrominance control 1; P97
{0x0f , 0x00}, //Chrominance gain control;
{0x10 , 0x00}, //Chrominance control 2; P98
{0x11 , 0x00}, //Mode/delay control;
{0x12 , 0xc9}, //0x00}, //0x8f}, //0xf8}, //0xd8}, //0xc7}, //RT signal control: RTS0[3:0]/PRS0[7:4] output; p99
{0x13 , 0x00}, //0x10}, //0x91}, //0x82}, //0x92}, //0x90}, //0x80}, //RT/X-port output control; p101
{0x14 , 0x00}, //Analog/ADC/compatibility control; p102
{0x15 , 0x15}, //0x00}, //VGATE pulse; FID polarity change; p103
{0x16 , 0x34}, //0x00}, //VGATE stop;
{0x17 , 0x02}, //0x00}, //Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0] p105
{0x18 , 0x40}, //Raw data gain control;
{0x19 , 0x80}, //Raw data offset control;
/* 0x1a - 0x1e, reserved*/
/* ...... */
{0x1f , 0x00}, //read only, Status byte video decoder; P106
/* 0x20 - 0x2f, reserved*/
/* ...... */
//Audio clock generation: 30H to 3FH
//AMCLK=256*32 kHZ=0x2000kHZ=8.192MHZ
{0x30 , 0x00}, //Audio master clock (AMCLK) cycles per field p106
{0x31 , 0x80}, //...
{0x32 , 0x02}, //... 0x30,0x31,0x32 --(FIELD:50HZ)ACPF= 0x28000HZ
{0x33 , 0x00}, //reserved
{0x34 , 0xab}, //Audio master clock (AMCLK) nominal increment p107
{0x35 , 0xaa}, //...
{0x36 , 0x2a}, //... 0x34,0x35,0x36 --(FIELD:50HZ)ACNI= 0x2aaaabHZ
{0x37 , 0x00}, // **** NO illuminate ****
{0x38 , 0x03}, //Clock ratio AMCLK (audio master clock) to ASCLK (serial bit clock)
{0x39 , 0x10}, //Clock ratio ASCLK (serial bit clock) to ALRCLK (channel select clock)
{0x3a , 0x00}, //Audio clock control;
/* 0x3b - 0x3f, reserved */
/* ...... */
//General purpose VBI-data slicer: 40H to 7FH
{0x40 , 0x00}, //Slicer control 1; p107
{0x41 , 0xff}, //Line control register; P108
{0x42 , 0xff}, //...
{0x44 , 0xff}, //...
{0x45 , 0xff}, //...
{0x46 , 0xff}, //...
{0x47 , 0xff}, //...
{0x48 , 0xff}, //...
{0x49 , 0xff}, //...
{0x4a , 0xff}, //...
{0x4b , 0xff}, //...
{0x4c , 0xff}, //...
{0x4d , 0xff}, //...
{0x4e , 0xff}, //...
{0x4f , 0xff}, //...
{0x50 , 0xff}, //...
{0x51 , 0xff}, //...
{0x52 , 0xff}, //...
{0x53 , 0xff}, //...
{0x54 , 0xff}, //...
{0x55 , 0xff}, //...
{0x56 , 0xff}, //...
{0x57 , 0xff}, //...
{0x58 , 0x40}, //Programmable framing code; P108
{0x59 , 0x47}, //Horizontal offset for slicer; slicer set 59H and 5BH
{0x5a , 0x03}, //Vertical offset for slicer; P109
{0x5b , 0x03}, //Field offset, and MSBs for horizontal and vertical offsets;
{0x5c , 0x00}, // **** NO illuminate ****
{0x5d , 0x00}, //Header and data identification (DID; ITU 656) code control;
{0x5e , 0x00}, //Sliced data identification (SDID) code;
{0x5f , 0x00}, // **** NO illuminate ****
{0x60 , 0x00}, //read only, Slicer status byte 0; P110
{0x61 , 0x00}, //read only, Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]
{0x62 , 0x00}, //read only
{0x63 , 0x00}, // **** NO illuminate ****
/* 0x64 - 0x7f, reserved*/
/* ...... */
//X-port, I-port and the scaler: 80H to EFH
{0x80 , 0x10}, //0x30}, //0x10}, //0x12}, //Global control 1; P110
{0x81 , 0x00}, // **** NO illuminate ****
{0x82 , 0x00}, // **** NO illuminate ****
{0x83 , 0x02}, //X-port I/O enable and output clock phase control; P110 - P115
{0x84 , 0xf4},//0xf0}, //I-port output signal definitions;
{0x85 , 0x00},//0x00}, //I-port reference signal polarities;
{0x86 , 0x45},//0x4f}, //I-port FIFO flag control and arbitration;
{0x87 , 0x01}, //0x02}, //port I/O enable, output clock and gated clock phase control;
{0x88 , 0xf0}, //0x01}, //Power save control; P115
{0x89 , 0x00}, // **** NO illuminate ****
{0x8a , 0x00}, // **** NO illuminate ****
{0x8b , 0x00}, // **** NO illuminate ****
{0x8c , 0x00}, // **** NO illuminate ****
{0x8d , 0x00}, // **** NO illuminate ****
{0x8e , 0x00}, // **** NO illuminate ****
{0x8f , 0x00}, //read only,Status information scaler part; P116
{0x90 , 0x04},//0x01},//0x06},//0x04}, //Task handling control; P117
{0x91 , 0x08},//0x08},//0x30}, //16-bit;X-port formats and configuration; P118
{0x92 , 0x10}, //X-port input reference signal definitions; P119
{0x93 , 0x0a},//0x88},//0x0a},//0x4a},//0x42},//0xc2}, //4:2:0; Dwords are transferred 16-bit word(93H[6]=1) or byte(93H[6]=0) wise;I-port output format and configuration; P120
{0x94 , 0x0a}, //Horizontal input window start; P121
{0x95 , 0x00}, //... (XO) 94H,95H = 16
{0x96 , 0xd0},//0xc0}, //Horizontal input window length;
{0x97 , 0x02}, //... (XS) 输入图象大小，720*576; 720=0x02d0
{0x98 , 0x14}, //Vertical input window start;
{0x99 , 0x00}, //... (YO) 98H,99H = 10
{0x9a , 0x22}, //Vertical input window length; 576/2 = 288;
{0x9b , 0x01}, //... (YS) 9aH,9bH = 0x0120+2 Decimal: 576/2+2;
{0x9c , 0x60},//0xc0}, //Horizontal output window length; P122
{0x9d , 0x01},//0x02}, //... (XD) 输出图象大小是:352*288; 352=0x0160
{0x9e , 0x20}, //Vertical output window length;
{0x9f , 0x01}, //... (YD) 288=0x0120
//0xa0 - 0xa7: Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H)
//0xa8 - 0xaf: Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH)
{0xa0 , 0x02},//0x01}, //Horizontal prescaling; P123
{0xa1 , 0x02},//0x00}, //?? Accumulation length;
{0xa2 , 0xaa},//0x00}, //?? Prescaler DC gain and FIR prefilter control;
{0xa3 , 0x00}, // **** NO illuminate ****
{0xa4 , 0x80},//0xa0}, //128;Luminance brightness setting; P124
{0xa5 , 0x40}, //64; Luminance contrast setting;
{0xa6 , 0x40}, //64; Chrominance saturation setting;
{0xa7 , 0x00}, // **** NO illuminate ****
{0xa8 , 0x18},//0x00},//0x5d},//0x18}, //Horizontal luminance scaling increment; P125
{0xa9 , 0x04}, //fisc*1024 = 1048 =0x0418
{0xaa , 0x00}, //Horizontal luminance phase offset;
{0xab , 0x00},
{0xac , 0x0c},//0x2e}, //Horizontal chrominance scaling increment;
{0xad , 0x02}, //524=0x020c; =1/2的Horizontal luminance scaling increment[A8,A9]
{0xae , 0x00}, //Horizontal chrominance phase offset;
{0xaf , 0x00},
{0xb0 , 0x00}, //Vertical luminance scaling increment; P126
{0xb1 , 0x04}, //vsc*1024 =2048 = 0x0800
{0xb2 , 0x00}, //Vertical chrominance scaling increment;
{0xb3 , 0x04}, //... 等于 [b0H,b1H]
{0xb4 , 0x00},//0x01}, //??Vertical scaling mode control;
{0xb5 , 0x00},
{0xb6 , 0x00},
{0xb7 , 0x00},
{0xb8 , 0x00}, //Vertical chrominance phase offset ‘00’;
{0xb9 , 0x00},
{0xba , 0x00},
{0xbb , 0x00},
{0xbc , 0x00}, //Vertical luminance phase offset ‘00’; P127
{0xbd , 0x00},
{0xbf , 0x00}
};
void SoftwareReset(PDEVICE_EXTENSION pDE, ULONG nChannel);
BOOLEAN Init7114(PDEVICE_EXTENSION pDE, int nChannel)
{
int i;
UCHAR VIPAddresses[2]={IIC_SUB_VIP,IIC_SUB_VIP2};
for(i=0; i<(sizeof(Reg7114Default)/sizeof(struct IICReg)); i++){
if(Reg7114Back[i].bySub==Reg7114Default[i].bySub) {
Reg7114Back[i].byData=Reg7114Default[i].byData;
}
IICWrite(pDE,VIPAddresses[nChannel],Reg7114Default[i].bySub,Reg7114Default[i].byData);
if(bIICError)
return FALSE;
}
//SoftWare Reset, 88H,bit SWRST
SoftwareReset(pDE,nChannel);
return TRUE;
}
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