📄 card.cpp
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#include "stdafx.h"
#include "number.h"
#include "card.h"
#include "boardreg.h"
//************PCI utility
CPciList g_PciList[64];
BOOL g_bWin98;
int g_nTotal;
#define PCI_CONFIG_PORT 0x00000cf8
#define PCI_DATA_PORT 0x00000cfc
#define MK_PCIADD(Bus,Dev,Func,Reg) \
(0x80000000|(((long)Bus)<<16)|(((long)Dev)<<11)|(((long)Func)<<8)|(Reg))
ULONG ReadPCICfgDWord(UCHAR nBus, UCHAR nDev, UCHAR nFun, UCHAR nRegAdd)
{
UCHAR nRegID;
USHORT wAddress=0;
ULONG lPciAdd;
ULONG lValue;
nRegID = nRegAdd & 0xfc;
wAddress = PCI_DATA_PORT + (nRegAdd & 0x03);
lPciAdd = MK_PCIADD(nBus, nDev, nFun, nRegID);
_asm{
cli
mov dx, PCI_CONFIG_PORT;
mov eax, lPciAdd;
out dx, eax;
//t_outpd(PCI_CONFIG_PORT,dwPciAdd);
mov dx, wAddress;
in eax, dx;
mov lValue, eax;
sti
}
//lValue = t_inpd(wAddress);
return lValue;
}
int FindPciDevices(CPciList* pList, ULONG uTarget)
{
ULONG uCode;
int nTotal=0;
for(int nBus=0; nBus<32; nBus++){
for(int nDev=0; nDev<0x16; nDev++){
uCode =ReadPCICfgDWord(nBus, nDev,0,0);
if (uCode==uTarget){
pList->nBus=nBus;
pList->nDev=nDev;
pList->nFun=0;
pList->uBasePort=ReadPCICfgDWord(nBus, nDev, 0, 0x10);
pList++;
nTotal++;
}
}
}
return nTotal;
}
int FindBusDev(CPciList *pPciList, int nTotal, ULONG Base, int *pBus, int *pSlot)
{
for(int i=0; i<nTotal; i++){
if(pPciList->uBasePort==Base){
*pBus=pPciList->nBus;
*pSlot=pPciList->nDev;
return 1;
}
pPciList++;
}
return 0;
}
BOOL CCard::OpenCard(int nCardNum)
{
CString DeviceName;
DeviceName.Format("\\\\.\\AVE2K%d",nCardNum);
m_hDevice = CreateFile(
/*"\\\\.\\AVE2K1",*/
DeviceName,
GENERIC_READ|GENERIC_WRITE,
0,
NULL,
OPEN_EXISTING,
FILE_ATTRIBUTE_NORMAL|FILE_FLAG_OVERLAPPED,
NULL );
if(m_hDevice == INVALID_HANDLE_VALUE)
return FALSE;
else{
OpenIIC();
//test 6kL alarm interface
//for(int i=0; i<100000; i++){
WriteReg(GPIO_CTRL, 0x40400000); //
WriteReg(GPIO_CTRL, 0x50400000); //relay 1
WriteReg(GPIO_CTRL, 0x40400000); //
WriteReg(GPIO_CTRL, 0x40500000);
WriteReg(GPIO_CTRL, 0x40400000);
//}
ULONG lPsr;
int nStatus;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
lPsr=ReadReg(PSR);
nStatus=(lPsr>>3)&0x03;
return TRUE;
}
}
BOOL CCard::CloseCard()
{
if(m_hDevice == INVALID_HANDLE_VALUE)
return FALSE;
CloseHandle(m_hDevice);
m_hDevice = INVALID_HANDLE_VALUE;
return TRUE;
}
void CCard::MicroDelay(ULONG delay)
{
ULONG i;
delay*=30;
if(delay<1)
delay=1;
for(i=0; i<delay; i++)
ReadReg(MC1);
}
ULONG CCard::ReadReg(ULONG n)
{
if(m_hDevice == INVALID_HANDLE_VALUE)
return 0xffffffff;
ULONG BytesWrite;
ULONG nRet;
DeviceIoControl(
m_hDevice,
IOCTL_READ_REGISTER,
&n,
sizeof(ULONG),
&nRet,
sizeof(ULONG),
&BytesWrite,
NULL);
return nRet;
}
BOOL CCard::WriteReg(ULONG n, ULONG nValue)
{
if(m_hDevice == INVALID_HANDLE_VALUE)
return FALSE;
ULONG BytesWrite;
int nTemp[2];
nTemp[0]=n;
nTemp[1]=nValue;
return DeviceIoControl(
m_hDevice,
IOCTL_WRITE_REGISTER,
nTemp,
sizeof(ULONG)*2,
NULL,
0,
&BytesWrite,
NULL);
}
BOOL CCard::GetBusSlot(int *pnBus, int *pnSlot)
{
if(m_hDevice == INVALID_HANDLE_VALUE)
return FALSE;
if(g_bWin98){
ULONG Base;
GetPortBase(&Base);
return FindBusDev(g_PciList, g_nTotal, Base, pnBus, pnSlot);
}
DWORD BytesWrites;
AVE2K_BOARD_INFO info;
BOOL n=DeviceIoControl(
m_hDevice,
IOCTL_BOARD_INFO,
NULL,
0,
&info,
sizeof(AVE2K_BOARD_INFO),
&BytesWrites,
NULL);
*pnBus=(info.Reserved>>12)&0x0f;
*pnSlot=(info.Reserved>>4)&0xff;
return n;
}
typedef struct{
ULONG uAddress;
ULONG uPortBase;
}CARD_ADDRESS;
BOOL CCard::GetPortBase(ULONG *pnBase)
{
if(m_hDevice == INVALID_HANDLE_VALUE)
return FALSE;
DWORD BytesWrites;
CARD_ADDRESS Address;
ULONG nTemp=0;
BOOL n=DeviceIoControl(
m_hDevice,
IOCTL_TRANSADDRESS,
&nTemp,
sizeof(ULONG),
&Address,
sizeof(ULONG)*2,
&BytesWrites,
NULL);
*pnBase=Address.uPortBase;
return n;
}
BOOL CCard::TransAddress(ULONG uVirAddress, PULONG puPhyAddress)
{
if(m_hDevice == INVALID_HANDLE_VALUE)
return FALSE;
DWORD BytesWrites;
CARD_ADDRESS Address;
BOOL n=DeviceIoControl(
m_hDevice,
IOCTL_TRANSADDRESS,
&uVirAddress,
sizeof(ULONG),
&Address,
sizeof(ULONG)*2,
&BytesWrites,
NULL);
*puPhyAddress=Address.uAddress;
return n;
}
CCard::CCard()
{
m_hDevice = INVALID_HANDLE_VALUE;
bIICError=FALSE;
}
void CCard::SetCardType(int nType, BOOL bRevD2)
{
switch(nType){
case TYPE_XD:
bCompress=TRUE;
bDouble=TRUE;
bVideoSrc=FALSE;
m_nBoardVersion=REVB2;
break;
case TYPE_XS:
case TYPE_III:
bCompress=TRUE;
bDouble=FALSE;
bVideoSrc=TRUE;
if(nType==0x2000)
m_nBoardVersion=REVA1;
else
m_nBoardVersion=REVA2;
break;
case TYPE_XQ:
case TYPE_XDPRO:
bCompress=TRUE;
bDouble=FALSE;
bVideoSrc=FALSE;
if(bRevD2)
m_nBoardVersion=REVD2;
else
m_nBoardVersion=REVD1;
break;
case TYPE_XSPRO:
bCompress=TRUE;
bDouble=FALSE;
bVideoSrc=FALSE;
m_nBoardVersion=REVD2;
break;
case TYPE_XM:
bCompress=FALSE;
bDouble=TRUE;
bVideoSrc=FALSE;
m_nBoardVersion=REVC2;
break;
case TYPE_SS3000:
m_nBoardVersion=REVSS3000;
bCompress=TRUE;
bDouble=FALSE;
bVideoSrc=TRUE;
break;
default:
bCompress=TRUE;
bDouble=TRUE;
bVideoSrc=TRUE;
m_nBoardVersion=REVA2;
break;
}
}
BOOL CCard::CheckCompress()
{
return bCompress;
}
BOOL CCard::CheckDouble()
{
return bDouble;
}
BOOL CCard::CheckVideoSrc()
{
return bVideoSrc;
}
#define A1_SWAP_YES 0x00200000
#define A2_SWAP_YES 0x00100000
#define A1_SWAP_NO 0x00000000
#define A2_SWAP_NO 0x00000000
#define WS_CTRL_INPUT 0l
#define WS_CTRL_3STATE 0l
#define WS_CTRL_OTSL1 1l
#define WS_CTRL_OTSL2 2l
#define WS_CTRL_OALOW 3l
#define WS_SYNC_I2S 0l
#define CLK_SRC_DIV8 7l
#define CLK_SRC_DIV6 6l
#define CLK_SRC_DIV4 5l
#define CLK_SRC1_BCLK1 0l
#define CLK_SRC1_BCLK2 1l
#define CLK_SRC2_BCLK1 1l
#define CLK_SRC2_BCLK2 0l
#define BCLK1_OE_YES 0
#define BCLK1_OE_NO (1l<<19)
#define BCLK2_OE_YES 0
#define BCLK2_OE_NO (1l<<18)
#define EOS 1
void CCard::ConfigAudio(ULONG BufferAdd)
{
unsigned long lAudioMode=3;
unsigned long lMaxLevel=127;
unsigned long lWS0,lWS1,lWS2,lWS3,lWS4;
unsigned long lAudioConfig1,lAudioConfig2;
WriteReg( MC1, EAP_YES); //Enable audio port pins
lWS0=(WS_CTRL_INPUT<<2)|WS_SYNC_I2S;
lAudioConfig2 = (CLK_SRC1_BCLK1<<27)|BCLK1_OE_NO;
if(m_nBoardVersion>=REVD1 || m_nBoardVersion==REVSS3000){
lWS4=(WS_CTRL_OTSL2<<2)|WS_SYNC_I2S;
if(m_nBoardVersion==REVSS3000)
lAudioConfig2 |=(CLK_SRC_DIV4<<22)|BCLK2_OE_YES;
else
lAudioConfig2 |=(CLK_SRC_DIV6<<22)|BCLK2_OE_YES;
}
else{
lWS4=(WS_CTRL_INPUT<<2)|WS_SYNC_I2S;
lAudioConfig2 |=(CLK_SRC2_BCLK2<<22)|BCLK2_OE_NO;
}
lWS1=lWS2=lWS3=(WS_CTRL_3STATE<<2)|WS_SYNC_I2S;
lAudioConfig1=(lAudioMode<<29)|(lMaxLevel<<22)|A1_SWAP_YES|A2_SWAP_YES| \
(lWS0<<16)|(lWS1<<12)|(lWS2<<8)|(lWS3<<4)|(lWS4);
WriteReg(ACON1,lAudioConfig1);
WriteReg(ACON2,lAudioConfig2);
if(!CheckDouble()){
WriteReg(TSL1_1,(0l<<31)|(1l<<24)|(0l<<23)|(3l<<15));
WriteReg(TSL1_2,(0l<<31)|(1l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_3,(0l<<31)|(1l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_4,(0l<<31)|(1l<<24)|(0l<<23)|(3l<<15));
WriteReg(TSL1_5,(1l<<31)|(1l<<24)|(0l<<23)|(3l<<15));
WriteReg(TSL1_6,(1l<<31)|(1l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_7,(1l<<31)|(1l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_8,(1l<<31)|(1l<<24)|(0l<<23)|(1l<<21)|(3l<<15)|EOS);
if(m_nBoardVersion==REVSS3000){
WriteReg(TSL2_1,(0l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_2,(0l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_3,(0l<<27)|(2l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_4,(0l<<27)|(2l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_5,(1l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_6,(1l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_7,(1l<<27)|(2l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_8,(1l<<27)|(2l<<11)|(0l<<10)|(3l<<2)|(1l<<8)|EOS);
}
else{
WriteReg(TSL2_1,(0l<<27)|(2l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_2,(0l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_3,(0l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_4,(0l<<27)|(2l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_5,(1l<<27)|(2l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_6,(1l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_7,(1l<<27)|(2l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_8,(1l<<27)|(2l<<11)|(0l<<10)|(3l<<2)|(1l<<8)|EOS);
}
}
else{
WriteReg(TSL1_1,(0l<<31)|(2l<<24)|(0l<<23)|(3l<<15));
WriteReg(TSL1_2,(0l<<31)|(2l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_3,(0l<<31)|(2l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_4,(0l<<31)|(2l<<24)|(0l<<23)|(3l<<15));
WriteReg(TSL1_5,(1l<<31)|(2l<<24)|(0l<<23)|(3l<<15));
WriteReg(TSL1_6,(1l<<31)|(2l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_7,(1l<<31)|(2l<<24)|(1l<<23)|(3l<<15));
WriteReg(TSL1_8,(1l<<31)|(2l<<24)|(0l<<23)|(1l<<21)|(3l<<15)|EOS);
WriteReg(TSL2_1,(0l<<27)|(1l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_2,(0l<<27)|(1l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_3,(0l<<27)|(1l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_4,(0l<<27)|(1l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_5,(1l<<27)|(1l<<11)|(0l<<10)|(3l<<2));
WriteReg(TSL2_6,(1l<<27)|(1l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_7,(1l<<27)|(1l<<11)|(1l<<10)|(3l<<2));
WriteReg(TSL2_8,(1l<<27)|(1l<<11)|(0l<<10)|(3l<<2)|(1l<<8)|EOS);
}
WriteReg(0x94, BufferAdd);
WriteReg(0x98, BufferAdd+2352);
//Set up interrupt limit : 2^10 = 1024
WriteReg( PAGE_A1_IN, (0x5<<4)/*|0x8*/ ); // bit 7-4, bit3: enable protection violation handling
WriteReg(0xac, BufferAdd);
WriteReg(0xb0, BufferAdd+2352);
//Set up interrupt limit : 2^10 = 1024
WriteReg( PAGE_A2_IN, (0x5<<4)/*|0x8*/ ); // bit 7-4, bit3: enable protection violation handling
}
void CCard::StartAudio(int nChannel)
{
if(nChannel==0)
WriteReg(MC1, 0x00040004);//audio DMA 2
else
WriteReg(MC1, 0x00010001);//audio DMA 1
}
void CCard::StopAudio()
{
WriteReg(MC1, 0x00050000);
}
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