brd_defs.inc

embed in keil

;====================================================================================|
;                                                                                    |
;                                System Board Defines                                |
;                                                                                    |
;  Filename :     Brd_defs.inc                                                       |
;  Author   :     A. Fuentes / 9051  ([e-mail])                   |
;  Date     :     October, 2001                                                      |
;                                                                                    |
;  Purpose:       Contains symbols and specific addresses used in the System Board   |
;                                                                                    |
;====================================================================================|

;<---[ Internal Data RAM addresses: ]------------------------------------------------>

FLAG       define   20h           ;Flag byte: first bit-addressable byte                

XMT_FLAG   define   FLAG.0        ;When set, denotes a block transmission in progress   
COD_FLAG   define   FLAG.1        ;When set, denotes a code download in progress         
CMD_FLAG   define   FLAG.2        ;When set, denotes a host command has been received   
INT_FLAG   define   FLAG.3        ;When set, denotes code download has been interrupted 
LOAD_END   define   FLAG.4        ;When set, denotes End-of-file reached (Intel HEX)  
LOAD_OK    define   FLAG.5        ;When set, denotes the code download was successful   

;<---[ Defines for RTOS kernel use: ]------------------------------------------------>

XSP        define   40h           ;40h-41h: Buffer of pointer to base of 'xstack'
TH0_BUFF   define   42h           ;Reload value for timer #0 (high)
TL0_BUFF   define   43h           ;Reload value for timer #0 (low)
WORK       define   44h           ;The subroutine work area ranges between 44h - 47h 
                                  ;This area is not preserved between calls

OS_TICKS_PER_SEC define  100      ;Timer #0 interrupts per second

T0_RLD     define   1000/OS_TICKS_PER_SEC    ;Number of milliseconds to trigger timer #0                         
T1_RLD     define   50                       ;Number of milliseconds to trigger timer #1                         
                                   
;<---[ External RAM addresses: ]----------------------------------------------------->
;
; The serial port reception buffer occupies the lower first KB in the second 64KB data
; bank.

BAUD_RATE      define   9600      ;Native serial port programmed speed 

RCV_BUFF       define   0A000h    ;Serial port receive buffer : A000h - A3FFh (1st KB)
XMT_BUFF       define   0A400h    ;Serial port transmit buffer: A400h - A7FFh (2nd KB) 

;<---[ PLD Internal Registers: ]----------------------------------------------------->

;<---[ Board External Registers: ]--------------------------------------------------->

;<---[ Port #1 dedicated pins: ]----------------------------------------------------->

;<---[ General purpose defines: ]---------------------------------------------------->

CR             define   0Dh       ;Carriage Return character
LF             define   0Ah       ;Line Feed character
EOL            define   1Ah       ;End-Of-Line character
ESC            define   1Bh       ;Escape character

NOERROR        define   00h       ;Return code for operation complete
OVERFLOW       define   01h       ;Return code when buffer full errors

;<---[ Internal processor register: ]------------------------------------------------>

Bk0_r0         define   00H       ;Bank 0, register 0 address
Bk0_r1         define   01H       ;Bank 0, register 1 address
Bk0_r2         define   02H       ;Bank 0, register 2 address
Bk0_r3         define   03H       ;Bank 0, register 3 address
Bk0_r4         define   04H       ;Bank 0, register 4 address
Bk0_r5         define   05H       ;Bank 0, register 5 address
Bk0_r6         define   06H       ;Bank 0, register 6 address
Bk0_r7         define   07H       ;Bank 0, register 7 address

Bk1_r0         define   08H       ;Bank 1, register 0 address
Bk1_r1         define   09H       ;Bank 1, register 1 address
Bk1_r2         define   0AH       ;Bank 1, register 2 address
Bk1_r3         define   0BH       ;Bank 1, register 3 address
Bk1_r4         define   0CH       ;Bank 1, register 4 address
Bk1_r5         define   0DH       ;Bank 1, register 5 address
Bk1_r6         define   0EH       ;Bank 1, register 6 address
Bk1_r7         define   0FH       ;Bank 1, register 7 address
                       
Bk2_r0         define   10H       ;Bank 2, register 0 address
Bk2_r1         define   11H       ;Bank 2, register 1 address
Bk2_r2         define   12H       ;Bank 2, register 2 address
Bk2_r3         define   13H       ;Bank 2, register 3 address
Bk2_r4         define   14H       ;Bank 2, register 4 address
Bk2_r5         define   15H       ;Bank 2, register 5 address
Bk2_r6         define   16H       ;Bank 2, register 6 address
Bk2_r7         define   17H       ;Bank 2, register 7 address

Bk3_r0         define   18H       ;Bank 3, register 0 address
Bk3_r1         define   19H       ;Bank 3, register 1 address
Bk3_r2         define   1AH       ;Bank 3, register 2 address
Bk3_r3         define   1BH       ;Bank 3, register 3 address
Bk3_r4         define   1CH       ;Bank 3, register 4 address
Bk3_r5         define   1DH       ;Bank 3, register 5 address
Bk3_r6         define   1EH       ;Bank 3, register 6 address
Bk3_r7         define   1FH       ;Bank 3, register 7 address