spim.tex

用汇编语言编程源代码

    \hline
  \end{tabular}
\end{center}
SPIM operates with both byte orders.  SPIM's byte order is determined
by the byte order of the underlying hardware running the simulator.
On a DECstation 3100, SPIM is little-endian, while on a HP Bobcat, Sun
4 or PC/RT, SPIM is big-endian.

\subsection {Addressing Modes}

MIPS is a load/store architecture, which means that only load and
store instructions access memory.  Computation instructions operate
only on values in registers.  The bare machine provides only one
memory addressing mode: {\tt c(rx)}, which uses the sum of the
immediate (integer) {\tt c} and the contents of register {\tt rx} as
the address.  The virtual machine provides the following addressing
modes for load and store instructions:
\begin{center}
  \small
  \begin{tabular}{|l|l|}
    \hline
    \multicolumn{1}{|c|}{\bf Format} &
	\multicolumn{1}{|c|}{\bf Address Computation} \\
    \hline
    \hline
    (register) &  contents of register \\
    imm & immediate \\
    imm (register) & immediate + contents of register \\
    symbol & address of symbol \\
    symbol $\pm$ imm & address of symbol $+$ or $-$ immediate \\
    symbol $\pm$ imm (register) & address of symbol $+$ or $-$
	(immediate + contents of register) \\
    \hline
  \end{tabular}
\end{center}

Most load and store instructions operate only on aligned data.  A
quantity is {\em aligned\/} if its memory address is a multiple of its
size in bytes.  Therefore, a halfword object must be stored at even
addresses and a full word object must be stored at addresses that are
a multiple of 4.  However, MIPS provides some instructions for
manipulating unaligned data.

\subsection {Arithmetic and Logical Instructions}

In all instructions below, {\tt Src2} can either be a register or an
immediate value (a 16 bit integer). The immediate forms of the
instructions are only included for reference.  The assembler will
translate the more general form of an instruction (e.g., {\tt add})
into the immediate form (e.g., {\tt addi}) if the second argument is
constant.

\pinst{abs Rdest, Rsrc}{Absolute Value}
Put the absolute value of the integer from register {\tt Rsrc} in
register {\tt Rdest}.

\inst{add Rdest, Rsrc1, Src2}{Addition (with overflow)}
\instX{addi Rdest, Rsrc1, Imm}{Addition Immediate (with overflow)}
\instX{addu Rdest, Rsrc1, Src2}{Addition (without overflow)}
\instX{addiu Rdest, Rsrc1, Imm}{Addition Immediate (without overflow)}
Put the sum of the integers from register {\tt Rsrc1} and {\tt
Src2} (or {\tt Imm}) into register {\tt Rdest}.

\inst{and Rdest, Rsrc1, Src2}{AND}
\instX{andi Rdest, Rsrc1, Imm}{AND Immediate}
Put the logical AND of the integers from register {\tt Rsrc1} and
{\tt Src2} (or {\tt Imm}) into register {\tt Rdest}.

\inst{div Rsrc1, Rsrc2}{Divide (signed)}
\instX{divu Rsrc1, Rsrc2}{Divide (unsigned)}
Divide the contents of the two registers.
{\tt divu} treats is operands as unsigned values.  Leave the quotient in
register {\tt lo} and the remainder in register {\tt hi}.  Note that
if an operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on which
SPIM is run.

\pinst{div Rdest, Rsrc1, Src2}{Divide (signed, with overflow)}
\pinstX{divu Rdest, Rsrc1, Src2}{Divide (unsigned, without overflow)}
Put the quotient of the integers from register {\tt Rsrc1} and {\tt
Src2} into register {\tt Rdest}. {\tt divu} treats is operands as
unsigned values.

\pinst{mul Rdest, Rsrc1, Src2}{Multiply (without overflow)}
\pinst{mulo Rdest, Rsrc1, Src2}{Multiply (with overflow)}
\pinstX{mulou Rdest, Rsrc1, Src2}{Unsigned Multiply (with overflow)}
Put the product of the integers from register {\tt Rsrc1} and {\tt
Src2} into register {\tt Rdest}.

\inst{mult Rsrc1, Rsrc2}{Multiply}
\instX{multu Rsrc1, Rsrc2}{Unsigned Multiply}
Multiply the contents of the two registers.  Leave the low-order word
of the product in register {\tt lo} and the high-word in register {\tt
hi}.

\pinst{neg Rdest, Rsrc}{Negate Value (with overflow)}
\pinstX{negu Rdest, Rsrc}{Negate Value (without overflow)}
Put the negative of the integer from register {\tt Rsrc} into
register {\tt Rdest}.

\inst{nor Rdest, Rsrc1, Src2}{NOR}
Put the logical NOR of the integers from register {\tt Rsrc1} and
{\tt Src2} into register {\tt Rdest}.

\pinst{not Rdest, Rsrc}{NOT}
Put the bitwise logical negation of the integer from register {\tt
Rsrc} into register {\tt Rdest}.

\inst{or Rdest, Rsrc1, Src2}{OR}
\instX{ori Rdest, Rsrc1, Imm}{OR Immediate}
Put the logical OR of the integers from register {\tt Rsrc1} and {\tt
Src2} (or {\tt Imm}) into register {\tt Rdest}.

\pinst{rem Rdest, Rsrc1, Src2}{Remainder}
\pinstX{remu Rdest, Rsrc1, Src2}{Unsigned Remainder}
Put the remainder from dividing the integer in register {\tt Rsrc1} by
the integer in {\tt Src2} into register {\tt Rdest}.  Note that if an
operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on which
SPIM is run.

\pinst{rol Rdest, Rsrc1, Src2}{Rotate Left}
\pinstX{ror Rdest, Rsrc1, Src2}{Rotate Right}
Rotate the contents of register {\tt Rsrc1} left (right) by the
distance indicated by {\tt Src2} and put the result in register
{\tt Rdest}.

\inst{sll Rdest, Rsrc1, Src2}{Shift Left Logical}
\instX{sllv Rdest, Rsrc1, Rsrc2}{Shift Left Logical Variable}
\instX{sra Rdest, Rsrc1, Src2}{Shift Right Arithmetic}
\instX{srav Rdest, Rsrc1, Rsrc2}{Shift Right Arithmetic Variable}
\instX{srl Rdest, Rsrc1, Src2}{Shift Right Logical}
\instX{srlv Rdest, Rsrc1, Rsrc2}{Shift Right Logical Variable}
Shift the contents of register {\tt Rsrc1} left (right) by the
distance indicated by {\tt Src2} ({\tt Rsrc2}) and put the
result in register {\tt Rdest}.

\inst{sub Rdest, Rsrc1, Src2}{Subtract (with overflow)}
\instX{subu Rdest, Rsrc1, Src2}{Subtract (without overflow)}
Put the difference of the integers from register {\tt Rsrc1} and {\tt
Src2} into register {\tt Rdest}.

\inst{xor Rdest, Rsrc1, Src2}{XOR}
\instX{xori Rdest, Rsrc1, Imm}{XOR Immediate}
Put the logical XOR of the integers from register {\tt Rsrc1} and
{\tt Src2} (or {\tt Imm}) into register {\tt Rdest}.


\subsection {Constant-Manipulating Instructions}

\pinst{li Rdest, imm}{Load Immediate}
Move the immediate {\tt imm} into register {\tt Rdest}.

\inst{lui Rdest, imm}{Load Upper Immediate}
Load the lower halfword of the immediate {\tt imm} into the upper
halfword of register {\tt Rdest}.  The lower bits of the register are
set to 0.


\subsection {Comparison Instructions}

In all instructions below, {\tt Src2} can either be a register or an
immediate value (a 16 bit integer).

\pinst{seq Rdest, Rsrc1, Src2}{Set Equal}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} equals {\tt
Src2} and to be 0 otherwise.

\pinst{sge Rdest, Rsrc1, Src2}{Set Greater Than Equal}
\pinstX{sgeu Rdest, Rsrc1, Src2}{Set Greater Than Equal Unsigned}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is greater
than or equal to {\tt Src2} and to 0 otherwise.

\pinst{sgt Rdest, Rsrc1, Src2}{Set Greater Than}
\pinstX{sgtu Rdest, Rsrc1, Src2}{Set Greater Than Unsigned}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is greater
than {\tt Src2} and to 0 otherwise.

\pinst{sle Rdest, Rsrc1, Src2}{Set Less Than Equal}
\pinstX{sleu Rdest, Rsrc1, Src2}{Set Less Than Equal Unsigned}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is less than
or equal to {\tt Src2} and to 0 otherwise.

\inst{slt Rdest, Rsrc1, Src2}{Set Less Than}
\instX{slti Rdest, Rsrc1, Imm}{Set Less Than Immediate}
\instX{sltu Rdest, Rsrc1, Src2}{Set Less Than Unsigned}
\instX{sltiu Rdest, Rsrc1, Imm}{Set Less Than Unsigned Immediate}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is less than
{\tt Src2} (or {\tt Imm}) and to 0 otherwise.

\pinst{sne Rdest, Rsrc1, Src2}{Set Not Equal}
Set register {\tt Rdest} to 1 if register {\tt Rsrc1} is not equal
to {\tt Src2} and to 0 otherwise.


\subsection {Branch and Jump Instructions}

In all instructions below, {\tt Src2} can either be a register or an
immediate value (integer).  Branch instructions use a signed 16-bit
offset field; hence they can jump $2^{15}-1$ {\em instructions\/} (not
bytes) forward or $2^{15}$ instructions backwards.  The {\em jump\/}
instruction contains a 26 bit address field.

\pinst{b label}{Branch instruction}
Unconditionally branch to the instruction at the label.

\inst{bc{\em z}t label}{Branch Coprocessor $z$ True}
\instX{bc{\em z}f label}{Branch Coprocessor $z$ False}
Conditionally branch to the instruction at the label if coprocessor
$z$'s condition flag is true (false).

\inst{beq Rsrc1, Src2, label}{Branch on Equal}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} equals {\tt Src2}.

\pinst{beqz Rsrc, label}{Branch on Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} equals 0.

\pinst{bge Rsrc1, Src2, label}{Branch on Greater Than Equal}
\pinstX{bgeu Rsrc1, Src2, label}{Branch on GTE Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are greater than or equal to {\tt Src2}.

\inst{bgez Rsrc, label}{Branch on Greater Than Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater than or equal to 0.

\inst{bgezal Rsrc, label}{Branch on Greater Than Equal Zero And Link}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater than or equal to 0. Save the address of
the next instruction in register 31.

\pinst{bgt Rsrc1, Src2, label}{Branch on Greater Than}
\pinstX{bgtu Rsrc1, Src2, label}{Branch on Greater Than Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are greater than {\tt Src2}.

\inst{bgtz Rsrc, label}{Branch on Greater Than Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater than 0.

\pinst{ble Rsrc1, Src2, label}{Branch on Less Than Equal}
\pinstX{bleu Rsrc1, Src2, label}{Branch on LTE Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are less than or equal to {\tt Src2}.

\inst{blez Rsrc, label}{Branch on Less Than Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are less than or equal to 0.

\inst{bgezal Rsrc, label}{Branch on Greater Than Equal Zero And Link}
\instX{bltzal Rsrc, label}{Branch on Less Than And Link}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are greater or equal to 0 or less than 0,
respectively. Save the address of the next instruction in register 31.

\pinst{blt Rsrc1, Src2, label}{Branch on Less Than}
\pinstX{bltu Rsrc1, Src2, label}{Branch on Less Than Unsigned}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are less than {\tt Src2}.

\inst{bltz Rsrc, label}{Branch on Less Than Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are less than 0.

\inst{bne Rsrc1, Src2, label}{Branch on Not Equal}
Conditionally branch to the instruction at the label if the contents
of register {\tt Rsrc1} are not equal to {\tt Src2}.

\pinst{bnez Rsrc, label}{Branch on Not Equal Zero}
Conditionally branch to the instruction at the label if the contents
of {\tt Rsrc} are not equal to 0.

\inst{j label}{Jump}
Unconditionally jump to the instruction at the label.

\inst{jal label}{Jump and Link}
\instX{jalr Rsrc}{Jump and Link Register}
Unconditionally jump to the instruction at the label or whose address
is in register {\tt Rsrc}.  Save the address of the next
instruction in register 31.

\inst{jr Rsrc}{Jump Register}
Unconditionally jump to the instruction whose address is in register
{\tt Rsrc}.


\subsection {Load Instructions}

\pinst{la Rdest, address}{Load Address}
Load computed {\em address\/}, not the contents of the location, into
register {\tt Rdest}.

\inst{lb Rdest, address}{Load Byte}
\instX{lbu Rdest, address}{Load Unsigned Byte}
Load the byte at {\em address\/} into register {\tt Rdest}.  The byte
is sign-extended by the {\tt lb}, but not the {\tt lbu}, instruction.

\pinst{ld Rdest, address}{Load Double-Word}
Load the 64-bit quantity at {\em address\/} into registers {\tt Rdest}
and {\tt Rdest + 1}.

\inst{lh Rdest, address}{Load Halfword}
\instX{lhu Rdest, address}{Load Unsigned Halfword}
Load the 16-bit quantity (halfword) at {\em address\/} into register
{\tt Rdest}.  The halfword is sign-extended by the {\tt lh}, but not
the {\bf lhu}, instruction

\inst{lw Rdest, address}{Load Word}
Load the 32-bit quantity (word) at {\em address\/} into register {\tt
Rdest}.

\inst{lwc{\em z\/} Rdest, address}{Load Word Coprocessor}
Load the word at {\em address\/} into register {\tt Rdest} of
coprocessor $z$ (0--3).

\inst{lwl Rdest, address}{Load Word Left}
\instX{lwr Rdest, address}{Load Word Right}
Load the left (right) bytes from the word at the possibly-unaligned
{\em address\/} into register {\tt Rdest}.

\pinst{ulh Rdest, address}{Unaligned Load Halfword}
\pinstX{ulhu Rdest, address}{Unaligned Load Halfword Unsigned}
Load the 16-bit quantity (halfword) at the possibly-unaligned {\em
address\/} into register {\tt Rdest}.  The halfword is sign-extended
by the {\tt ulh}, but not the {\bf ulhu}, instruction

\pinst{ulw Rdest, address}{Unaligned Load Word}
Load the 32-bit quantity (word) at the possibly-unaligned {\em
address\/}  into register {\tt Rdest}.


\subsection {Store Instructions}

\inst{sb Rsrc, address}{Store Byte}
Store the low byte from register {\tt Rsrc} at {\em address\/}.

\pinst{sd Rsrc, address}{Store Double-Word}
Store the 64-bit quantity in registers {\tt Rsrc} and {\tt Rsrc
+ 1} at {\em address\/}.

\inst{sh Rsrc, address}{Store Halfword}
Store the low halfword from register {\tt Rsrc} at {\em address\/}.

\inst{sw Rsrc, address}{Store Word}
Store the word from register {\tt Rsrc} at {\em address\/}.

\inst{swc{\em z\/} Rsrc, address}{Store Word Coprocessor}
Store the word from register {\tt Rsrc} of coprocessor $z$ at
{\em address\/}.

\inst{swl Rsrc, address}{Store Word Left}
\instX{swr Rsrc, address}{Store Word Right}
Store the left (right) bytes from register {\tt Rsrc} at the
possibly-unaligned {\em address\/}.

\pinst{ush Rsrc, address}{Unaligned Store Halfword}