spim.tex

用汇编语言编程源代码

Everything from the sharp-sign to the end of the line is ignored.

Identifiers are a sequence of alphanumeric characters, underbars ({\tt
\_}), and dots ({\tt .}) that do not begin with a number.  Opcodes for
instructions are reserved words that are {\bf not} valid identifiers.
Labels are declared by putting them at the beginning of a line
followed by a colon, for example:
\begin{verbatim}
        .data
  item: .word 1
        .text
        .globl main             # Must be global
  main: lw $t0, item
\end{verbatim}

Strings are enclosed in double-quotes ({\tt "}).  Special characters
in strings follow the C convention:
\begin{verbatim}
    newline        \n
    tab            \t
    quote          \"
\end{verbatim}

SPIM supports a subset of the assembler directives provided by the
MIPS assembler:
\begin{description}
  \item [] {\tt .align n}\newline Align the next datum on a $2^n$ byte
boundary.  For example, {\tt .align 2} aligns the next value on a word
boundary.  {\tt .align 0} turns off automatic alignment of {\tt
.half}, {\tt .word}, {\tt .float}, and {\tt .double} directives until
the next {\tt .data} or {\tt .kdata} directive.

  \item [] {\tt .ascii str}\newline Store the string in memory, but do
not null-terminate it.

  \item [] {\tt .asciiz str}\newline Store the string in memory and
null-terminate it.

  \item [] {\tt .byte b1, ..., bn}\newline Store the $n$ values in
successive bytes of memory.

  \item [] {\tt .data <addr>}\newline The following data items should
be stored in the data segment.  If the optional argument {\em addr\/}
is present, the items are stored beginning at address {\em addr\/}.

  \item [] {\tt .double d1, ..., dn}\newline Store the $n$ floating
point double precision numbers in successive memory locations.

  \item [] {\tt .extern sym size}\newline Declare that the datum
stored at {\tt sym} is {\tt size} bytes large and is a global symbol.
This directive enables the assembler to store the datum in a portion
of the data segment that is efficiently accessed via register {\tt
\$gp}.

  \item [] {\tt .float f1, ..., fn}\newline Store the $n$ floating
point single precision numbers in successive memory locations.

  \item [] {\tt .globl sym}\newline Declare that symbol {\tt sym} is
global and can be referenced from other files.

  \item [] {\tt .half h1, ..., hn}\newline Store the $n$ 16-bit
quantities in successive memory halfwords.

  \item [] {\tt .kdata <addr>}\newline The following data items should
be stored in the kernel data segment. If the optional argument {\em
addr\/} is present, the items are stored beginning at address {\em
addr\/}.

  \item [] {\tt .ktext <addr>}\newline The next items are put in the
kernel text segment.  In SPIM, these items may only be instructions or
words (see the {\tt .word} directive below). If the optional argument
{\em addr\/} is present, the items are stored beginning at address
{\em addr\/}.

  \item [] {\tt .space n}\newline Allocate $n$ bytes of space in the
current segment (which must be the data segment in SPIM).

  \item [] {\tt .text <addr>}\newline The next items are put in the
user text segment.  In SPIM, these items may only be instructions or
words (see the {\tt .word} directive below).  If the optional argument
{\em addr\/} is present, the items are stored beginning at address
{\em addr\/}.

  \item [] {\tt .word w1, ..., wn}\newline Store the $n$ 32-bit
quantities in successive memory words.
\end{description}
SPIM does not distinguish various parts of the data segment ({\tt
.data}, {\tt .rdata}, and {\tt .sdata}).

\subsection{System Calls}
\label{sec:scall}

\begin{table}
  \small
  \begin{center}
  \begin{tabular}{|l|c|l|l|}
    \hline
     \multicolumn{1}{|c|}{\bf Service} &
	{\bf System Call Code} &
	\multicolumn{1}{|c|}{\bf Arguments} &
	\multicolumn{1}{|c|}{\bf Result} \\
     \hline
     \hline
      print\_int & 1 & {\tt \$a0} = integer & \\
      print\_float & 2 & {\tt \$f12} = float & \\
      print\_double & 3 & {\tt \$f12} = double & \\
      print\_string & 4 & {\tt \$a0} = string & \\
      read\_int & 5 & & integer (in {\tt \$v0}) \\
      read\_float & 6 & & float (in {\tt \$f0}) \\
      read\_double & 7 & & double (in {\tt \$f0}) \\
      read\_string & 8 & {\tt \$a0} = buffer, {\tt \$a1} = length & \\
      sbrk & 9 & {\tt \$a0} = amount & address (in {\tt \$v0}) \\
      exit & 10 & & \\
      print\_character & 11 & {\tt \$a0} = integer & \\
      read\_character & 12 & char (in {\tt \$v0}) \\
     \hline
  \end{tabular}
  \end{center}
  \caption{System services.}
  \label{tab:syscall}
\end{table}
SPIM provides a small set of operating-system-like services through
the system call ({\tt syscall}) instruction.  To request a service, a
program loads the system call code (see Table~\ref{tab:syscall}) into
register {\tt \$v0} and the arguments into registers {\tt
\$a0}$\ldots${\tt \$a3} (or {\tt \$f12} for floating point values).
System calls that return values put their result in register {\tt
\$v0} (or {\tt \$f0} for floating point results).  For example, to
print ``{\tt the answer = 5}'', use the commands:
\begin{verbatim}
        .data
  str:  .asciiz "the answer = "
        .text
        li $v0, 4        # system call code for print_str
        la $a0, str      # address of string to print
        syscall          # print the string

        li $v0, 1        # system call code for print_int
        li $a0, 5        # integer to print
        syscall          # print it
\end{verbatim}

{\tt print\_int} is passed an integer and prints it on the console.
{\tt print\_float} prints a single floating point number. {\tt
print\_double} prints a double precision number.  {\tt print\_string}
is passed a pointer to a null-terminated string, which it writes to
the console.

{\tt read\_int}, {\tt read\_float}, and {\tt read\_double} read an
entire line of input up to and including the newline.  Characters
following the number are ignored.  {\tt read\_string} has the same
semantics as the Unix library routine {\tt fgets}.  It reads up to
$n-1$ characters into a buffer and terminates the string with a null
byte.  If there are fewer characters on the current line, it reads
through the newline and again null-terminates the string.  {\bf
Warning:} programs that use these syscalls to read from the terminal
should not use memory-mapped IO (see Section~\ref{sec:IO}).

{\tt sbrk} returns a pointer to a block of memory containing $n$
additional bytes.  {\tt exit} stops a program from running.

\section{Description of the MIPS R2000}
\label{sec:mips}

\begin{figure}
  \centerline{\psfig{figure=mips.id,height=4in}}
  \caption{MIPS R2000 CPU and FPU}
  \label{fig:mips}
\end{figure}
A MIPS processor consists of an integer processing unit (the CPU) and
a collection of coprocessors that perform ancillary tasks or operate
on other types of data such as floating point numbers (see
Figure~\ref{fig:mips}).  SPIM simulates two coprocessors.  Coprocessor
0 handles traps, exceptions, and the virtual memory system.  SPIM
simulates most of the first two and entirely omits details of the
memory system.  Coprocessor 1 is the floating point unit.  SPIM
simulates most aspects of this unit.

\subsection{CPU Registers}

\begin{table}
  \small
  \begin{center}
  \begin{tabular}{|l|r|l|}
    \hline
     {\bf Register Name} & {\bf Number} & \multicolumn{1}{|c|}{\bf Usage} \\
     \hline
     \hline
      zero & 0 & Constant 0 \\
      at & 1 & Reserved for assembler \\
      v0 & 2 & Expression evaluation and \\
      v1 & 3 & \ \ \ \ results of a function \\
      a0 & 4 & Argument 1 \\
      a1 & 5 & Argument 2 \\
      a2 & 6 & Argument 3 \\
      a3 & 7 & Argument 4 \\
      t0 & 8 & Temporary (not preserved across call) \\
      t1 & 9 & Temporary (not preserved across call) \\
      t2 & 10 & Temporary (not preserved across call) \\
      t3 & 11 & Temporary (not preserved across call) \\
      t4 & 12 & Temporary (not preserved across call) \\
      t5 & 13 & Temporary (not preserved across call) \\
      t6 & 14 & Temporary (not preserved across call) \\
      t7 & 15 & Temporary (not preserved across call) \\
      s0 & 16 & Saved temporary (preserved across call) \\
      s1 & 17 & Saved temporary (preserved across call) \\
      s2 & 18 & Saved temporary (preserved across call) \\
      s3 & 19 & Saved temporary (preserved across call) \\
      s4 & 20 & Saved temporary (preserved across call) \\
      s5 & 21 & Saved temporary (preserved across call) \\
      s6 & 22 & Saved temporary (preserved across call) \\
      s7 & 23 & Saved temporary (preserved across call) \\
      t8 & 24 & Temporary (not preserved across call) \\
      t9 & 25 & Temporary (not preserved across call) \\
      k0 & 26 & Reserved for OS kernel \\
      k1 & 27 & Reserved for OS kernel \\
      gp & 28 & Pointer to global area \\
      sp & 29 & Stack pointer \\
      fp & 30 & Frame pointer \\
      ra & 31 & Return address (used by function call) \\
     \hline
  \end{tabular}
  \end{center}
  \caption{MIPS registers and the convention governing their use.}
  \label{tab:reg}
\end{table}

The MIPS (and SPIM) central processing unit contains 32 general
purpose 32-bit registers that are numbered 0--31.  Register $n$ is designated
by {\tt \$n}.  Register {\tt \$0} always contains the hardwired value
0.  MIPS has established a set of conventions as to how registers
should be used.  These suggestions are guidelines, which are not
enforced by the hardware.  However a program that violates them will
not work properly with other software.  Table~\ref{tab:reg} lists the
registers and describes their intended use.

Registers {\tt \$at} (1), {\tt \$k0} (26), and {\tt \$k1} (27) are
reserved for use by the assembler and operating system.

Registers {\tt \$a0}--{\tt \$a3} (4--7) are used to pass the first
four arguments to routines (remaining arguments are passed on the
stack).  Registers {\tt \$v0} and {\tt \$v1} (2, 3) are used to return
values from functions.  Registers {\tt \$t0}--{\tt \$t9} (8--15, 24,
25) are caller-saved registers used for temporary quantities that do
not need to be preserved across calls.  Registers {\tt \$s0}--{\tt
\$s7} (16--23) are callee-saved registers that hold long-lived values
that should be preserved across calls.

Register {\tt \$sp} (29) is the stack pointer, which points to the last
location in use on the stack.\footnote{In earlier version of SPIM, {\tt
\$sp} was documented as pointing at the first free word on the stack (not
the last word of the stack frame).  Recent MIPS documents have made it clear
that this was an error.  Both conventions work equally well, but we choose
to follow the real system.}  Register {\tt \$fp} (30) is the frame
pointer.\footnote{The MIPS compiler does not use a frame pointer, so this
register is used as callee-saved register {\tt \$s8}.} Register {\tt \$ra}
(31) is written with the return address for a call by the {\tt jal}
instruction.

Register {\tt \$gp} (28) is a global pointer that points into the
middle of a 64K block of memory in the heap that holds constants and
global variables.  The objects in this heap can be quickly accessed
with a single load or store instruction.

In addition, coprocessor 0 contains registers that are useful to
handle exceptions.  SPIM does not implement all of these registers,
since they are not of much use in a simulator or are part of the
memory system, which is not implemented.  However, it does provide the
following:
\begin{center}
  \small
  \begin{tabular}{|l|c|l|}
    \hline
    {\bf Register Name} & {\bf Number} & \multicolumn{1}{|c|}{\bf Usage} \\
    \hline
    \hline
    BadVAddr & 8 & Memory address at which address exception occurred \\
    Status & 12 & Interrupt mask and enable bits \\
    Cause & 13 & Exception type and pending interrupt bits \\
    EPC & 14 & Address of instruction that caused exception \\
    \hline
  \end{tabular}
\end{center}
These registers are part of coprocessor 0's register set and are
accessed by the {\tt lwc0}, {\tt mfc0}, {\tt mtc0}, and {\tt swc0}
instructions.

\begin{figure}
  \centerline{\psfig{figure=status_reg.id}}
  \caption{The {\tt Status} register.}
  \label{fig:status_reg}
\end{figure}
\begin{figure}
  \centerline{\psfig{figure=cause_reg.id}}
  \caption{The {\tt Cause} register.}
  \label{fig:cause_reg}
\end{figure}
Figure~\ref{fig:status_reg} describes the bits in the {\tt Status}
register that are implemented by SPIM.  The {\tt interrupt mask}
contains a bit for each of the five interrupt levels.  If a bit is
one, interrupts at that level are allowed.  If the bit is zero,
interrupts at that level are disabled.  The low six bits of the {\tt
Status} register implement a three-level stack for the {\tt
kernel/user} and {\tt interrupt enable} bits.  The {\tt kernel/user}
bit is 0 if the program was running in the kernel when the interrupt
occurred and 1 if it was in user mode. If the {\tt interrupt enable}
bit is 1, interrupts are allowed.  If it is 0, they are disabled. At an
interrupt, these six bits are shifted left by two bits, so the current
bits become the previous bits and the previous bits become the old
bits.  The current bits are both set to 0 (i.e., kernel mode with
interrupts disabled).

Figure~\ref{fig:cause_reg} describes the bits in the {\tt Cause}
registers.  The five {\tt pending interrupt} bits correspond to the
five interrupt levels.  A bit becomes 1 when an interrupt at its level
has occurred but has not been serviced.  The {\tt exception code}
register contains a code from the following table describing the cause
of an exception.
\begin{center}
  \small
  \begin{tabular}{|l|l|l|}
    \hline
    {\bf Number} & {\bf Name} & {\bf Description} \\
    \hline
    \hline
    0 & INT & External interrupt \\
    4 & ADDRL & Address error exception (load or instruction fetch) \\
    5 & ADDRS & Address error exception (store) \\
    6 & IBUS & Bus error on instruction fetch \\
    7 & DBUS & Bus error on data load or store \\
    8 & SYSCALL & Syscall exception \\
    9 & BKPT & Breakpoint exception \\
    10&  RI & Reserved instruction exception \\
    12&  OVF & Arithmetic overflow exception \\
    \hline
  \end{tabular}
\end{center}

\subsection{Byte Order}

Processors can number the bytes within a word to make the byte with
the lowest number either the leftmost or rightmost one.  The convention
used by a machine is its {\em byte order\/}.  MIPS processors can
operate with either {\em big-endian\/} byte order:
\begin{center}
  \begin{tabular}{|c|c|c|c|}
    \multicolumn{4}{c}{{\bf Byte \#}} \\
    \hline
    0 & 1 & 2 & 3 \\
    \hline
  \end{tabular}
\end{center}
or {\em little-endian\/} byte order:
\begin{center}
  \begin{tabular}{|c|c|c|c|}
    \multicolumn{4}{c}{{\bf Byte \#}} \\
    \hline
    3 & 2 & 1 & 0 \\