mdk_tut.texi

汇编语言编程源代码

@c -*-texinfo-*-
@c This is part of the GNU MDK Reference Manual.
@c Copyright (C) 2000, 2001, 2002
@c   Free Software Foundation, Inc.
@c See the file mdk.texi for copying conditions.

@c $Id: mdk_tut.texi,v 1.7 2002/04/08 00:26:37 jao Exp $

@node MIX and MIXAL tutorial, Getting started, Installing MDK, Top
@comment  node-name,  next,  previous,  up
@chapter MIX and MIXAL tutorial
@cindex MIX
@cindex MIXAL

In the book series @cite{The Art of Computer Programming}, by D. Knuth,
a virtual computer, the MIX, is used by the author (together with the
set of binary instructions that the virtual CPU accepts) to illustrate
the algorithms and skills that every serious programmer should
master. Like any other real computer, there is a symbolic assembler
language that can be used to program the MIX: the MIX assembly language,
or MIXAL for short.  In the following subsections you will find a tutorial
on these topics, which will teach you the basics of the MIX architecture
and how to program a MIX computer using MIXAL.

@menu
* The MIX computer::            Architecture and instruction set 
                                of the MIX computer.
* MIXAL::                       The MIX assembly language.
@end menu

@node The MIX computer, MIXAL, MIX and MIXAL tutorial, MIX and MIXAL tutorial
@comment  node-name,  next,  previous,  up
@section The MIX computer

In this section, you will find a description of the MIX computer,
its components and instruction set.

@menu
* MIX architecture::            
* MIX instruction set::         
@end menu

@node MIX architecture, MIX instruction set, The MIX computer, The MIX computer
@comment  node-name,  next,  previous,  up
@subsection MIX architecture
@cindex byte
@cindex MIX byte
@cindex word
@cindex MIX word
@cindex MIX architecture
@cindex MIX computer
@cindex register
@cindex MIX register
@cindex field specification
@cindex fspec
@cindex instruction
@cindex MIX instruction
@cindex address
@cindex memory cell
@cindex cell
@cindex memory
@cindex index

The basic information storage unit in the MIX computer is the
@dfn{byte}, which stores positive values in the range 0-63 . Note that a
MIX byte can be then represented as 6 bits, instead of the common 8 bits
for a @emph{regular} byte. Unless otherwise stated, we shall use the
word @dfn{byte} to refer to a MIX 6-bit byte.

A MIX @dfn{word} is defined as a set of 5 bytes plus a sign. The bytes
within a word are numbered from 1 to 5, being byte number one the most
significant one. The sign is denoted by index 0. Graphically,

@example
 -----------------------------------------------
|   0   |   1   |   2   |   3   |   4   |   5   |
 -----------------------------------------------
|  +/-  | byte  | byte  | byte  | byte  | byte  |     
 -----------------------------------------------
@end example
@noindent
Sample MIX words are @samp{- 12 00 11 01 63} and @samp{+ 12 11 34 43
00}.

You can refer to subfields within a word using a @dfn{field
specification} or @dfn{fspec} of the form ``(@var{L}:@var{R})'', where
@var{L} denotes the first byte, and @var{R} the last byte of the
subfield.
When @var{L} is zero, the subfield includes the word's
sign. An fspec can also be represented as a single value @code{F}, given
by @code{F = 8*L + R} (thus the fspec @samp{(1:3)}, denoting the first
three bytes of a word, is represented by the integer 11).

The MIX computer stores information in @dfn{registers}, that can store
either a word or two bytes and sign (see below), and @dfn{memory cells},
each one containing a word. Specifically, the MIX computer has 4000
memory cells with addresses 0 to 3999 (i.e., two bytes are enough to
address a memory cell) and the following registers:

@cindex rA
@cindex rX
@cindex rJ
@cindex rIn
@cindex register

@table @asis
@item @code{rA}
A register. General purpose register holding a word. Usually its
contents serves as the operand of arithmetic and storing instructions.
@item @code{rX}
X register. General purpose register holding a word. Often it acts as an
extension or a replacement of @samp{rA}.
@item @code{rJ}
J (jump) register. This register stores positive two-byte values,
usually representing a jump address.
@item @code{rI1}, @code{rI2}, @code{rI3}, @code{rI4}, @code{rI5}, @code{rI6}
Index registers. These six registers can store a signed two-byte
value. Their contents are used as indexing values for the computation of
effective memory addresses.
@end table

@cindex @sc{ov}
@cindex @sc{cm}
@cindex @code{un}
@cindex overflow toggle
@cindex comparison indicator
@cindex input-output devices
@noindent
In addition, the MIX computer contains:

@itemize @minus
@item
An @dfn{overflow toggle} (a single bit with values @dfn{on} or
@dfn{off}). In this manual, this toggle is denoted @sc{ov}.
@item
A @dfn{comparison indicator} (having three values: @dfn{EQUAL},
@dfn{GREATER} or @dfn{LESS}). In this manual, this indicator is denoted
@sc{cm}, and its possible values are abbreviated as @dfn{E}, @dfn{G} and
@dfn{L}.
@item
Input-output block devices. Each device is labelled as @code{un}, where
@code{n} runs from 0 to 20. In Knuth's definition, @code{u0} through
@code{u7} are magnetic tape units, @code{u8} through @code{15} are disks
and drums, @code{u16} is a card reader, @code{u17} is a card writer,
@code{u18} is 
a line printer and, @code{u19} is a typewriter terminal, and @code{u20},
a paper tape. Our implementation maps these devices to disk files,
except for @code{u19}, which represents the standard output.
@end itemize

As noted above, the MIX computer communicates with the external world by
a set of input-output devices which can be ``connected'' to it. The
computer interchanges information using blocks of words whose length
depends on the device at hand (@pxref{Devices}). These words are
interpreted by the device either as binary information (for devices
0-16), or as representing printable characters (devices 17-20). In the
last case, each MIX byte is mapped onto a character according to the
following table:

@multitable  {00} {C} {00} {C} {00} {C} {00} {C}
@item  00 @tab  @tab 01 @tab A @tab 02 @tab B @tab 03 @tab C
@item  04 @tab D @tab 05 @tab E @tab 06 @tab F @tab 07 @tab G
@item  08 @tab H @tab 09 @tab I @tab 10 @tab d @tab 11 @tab J
@item  12 @tab K @tab 13 @tab L @tab 14 @tab M @tab 15 @tab N
@item  16 @tab O @tab 17 @tab P @tab 18 @tab Q @tab 19 @tab R
@item  20 @tab s @tab 21 @tab p @tab 22 @tab S @tab 23 @tab T
@item  24 @tab U @tab 25 @tab V @tab 26 @tab W @tab 27 @tab X
@item  28 @tab Y @tab 29 @tab Z @tab 30 @tab 0 @tab 31 @tab 1 
@item  32 @tab 2 @tab 33 @tab 3 @tab 34 @tab 4 @tab 35 @tab 5
@item  36 @tab 6 @tab 37 @tab 7 @tab 38 @tab 8 @tab 39 @tab 9
@item  40 @tab . @tab 41 @tab , @tab 42 @tab ( @tab 43 @tab )
@item  44 @tab + @tab 45 @tab - @tab 46 @tab * @tab 47 @tab /
@item  48 @tab = @tab 49 @tab $ @tab 50 @tab < @tab 51 @tab >
@item  52 @tab @@ @tab 53 @tab ; @tab 54 @tab : @tab 55 @tab '
@end multitable
@noindent
The value 0 represents a whitespace. Lowercase letters (d, s, p)
correspond to symbols not representable as ASCII characters (uppercase
delta, sigma and gamma, respectively), and byte values 56-63 have no
associated character.

Finally, the MIX computer features a virtual CPU which controls the
above components, and which is able to execute a rich set of
instructions (constituting its machine language, similar to those
commonly found in real CPUs), including arithmetic, logical, storing,
comparison and jump instructions. Being a typical von Neumann computer,
the MIX CPU fetchs binary instructions from memory sequentially (unless
a jump instruction is found), and stores the address of the next
instruction to be executed in an internal register called @dfn{location
counter} (also known as program counter in other architectures).

The next section, @xref{MIX instruction set}, gives a complete description
of the available MIX binary instructions.

@node MIX instruction set,  , MIX architecture, The MIX computer
@comment  node-name,  next,  previous,  up
@subsection MIX instruction set
@cindex instruction set

The following subsections fully describe the instruction set of the MIX
computer. We begin with a description of the structure of binary
instructions and the notation used to refer to their subfields. The
remaininig subsections are devoted to describing the actual instructions
available to the MIX programmer.

@menu
* Instruction structure::       
* Loading operators::           
* Storing operators::           
* Arithmetic operators::        
* Address transfer operators::  
* Comparison operators::        
* Jump operators::              
* Input-output operators::      
* Conversion operators::        
* Shift operators::             
* Miscellaneous operators::     
* Execution times::             
@end menu

@node Instruction structure, Loading operators, MIX instruction set, MIX instruction set
@comment  node-name,  next,  previous,  up
@subsubsection Instruction structure

MIX @dfn{instructions} are codified as words with the following subfield
structure:

@multitable @columnfractions .15 .20 .65
@item @emph{Subfield} @tab @emph{fspec} @tab @emph{Description}
@item ADDRESS @tab (0:2)
@tab The first two bytes plus sign are the @dfn{address} field. Combined
with the INDEX field, denotes the memory address to be used by the
instruction.
@item INDEX @tab (3:3)
@tab The third byte is the @dfn{index}, normally used for indexing the
address@footnote{The actual memory address the instruction refers to, is
obtained by adding to ADDRESS the value of the @samp{rI} register
denoted by INDEX.}.
@item MOD @tab (4:4)
@tab Byte four is used either as an operation code modifier or as a field
specification.
@item OPCODE @tab (5:5)
@tab The last (least significant) byte in the word denotes the operation
code.
@end multitable

@noindent
or, graphically,

@example
 ------------------------------------------------
|   0   |   1   |   2   |   3   |   4   |   5    |
 ------------------------------------------------
|        ADDRESS        | INDEX |  MOD  | OPCODE |     
 ------------------------------------------------
@end example

For a given instruction, @samp{M} stands for
the memory address obtained after indexing the ADDRESS subfield 
(using its INDEX byte), and @samp{V} is the contents of the
subfield indicated by MOD of the memory cell with address @samp{M}. For
instance, suppose that we have the following contents of MIX registers
and memory cells:

@example
[rI2] = + 00 63
[31] = - 10 11 00 11 22
@end example
@noindent
where @samp{[n]} denotes the contents of the nth memory cell and
@samp{[rI2]} the contents of register @samp{rI2}@footnote{In general,
@samp{[X]} will denote the contents of entity @samp{X}; thus, by
definition, @w{@samp{V = [M](MOD)}}.}.  Let us consider the binary
instruction @w{@samp{I = - 00 32 02 11 10}}. For this instruction we
have:

@example
ADDRESS = - 00 32 = -32
INDEX = 02 = 2
MOD = 11 = (1:3)
OPCODE = 10

M = ADDRESS + [rI2] = -32 + 63 = 31
V = [M](MOD) = (- 10 11 00 11 22)(1:3) = + 00 00 10 11 00
@end example

Note that, when computing @samp{V} using a word and an fspec, we apply
a left padding to the bytes selected by @samp{MOD} to obtain a
complete word as the result. 

In the following subsections, we will
assing to each MIX instruction a mnemonic, or symbolic name. For
instance, the mnemonic of @samp{OPCODE} 10 is @samp{LD2}. Thus we can
rewrite the above instruction as

@example
LD2  -32,2(1:3)
@end example
@noindent
or, for a generic instruction:

@example
MNEMONIC  ADDRESS,INDEX(MOD)
@end example
@noindent
Some instructions are identified by both the OPCODE and the MOD
fields. In these cases, the MOD will not appear in the above symbolic
representation. Also when ADDRESS or INDEX are zero, they can be
omitted.  Finally, MOD defaults to (0:5) (meaning the
whole word).

@node Loading operators, Storing operators, Instruction structure, MIX instruction set
@comment  node-name,  next,  previous,  up
@subsubsection Loading operators
@cindex loading operators

The following instructions are used to load memory contents into a
register.

@ftable @code
@item LDA
Put in rA the contents of cell no. M.
OPCODE = 8, MOD = fspec. @code{rA <- V}.
@item LDX
Put in rX the contents of cell no. M.