📄 d14.h
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//***********************************************************************
// *
// P H I L I P S P R O P R I E T A R Y *
// *
// COPYRIGHT (c) 1999 BY PHILIPS SINGAPORE (APIC). *
// -- ALL RIGHTS RESERVED -- *
// *
// File Name : D14.h *
// Author : Albert Goh *
// Created : 3 March 2000 *
// *
//***********************************************************************
//***********************************************************************
// *
// Kernel.h has the various external defintion and structure defintion *
// *
//***********************************************************************
//***********************************************************************
// *
// Module History *
// ************** *
// *
// Date Version Author Changes *
// ==== ======= ====== ======= *
// 030300 0.1 Albert Created *
// *
// *
//***********************************************************************
//***********************************************************************
//* *
//* Structure Variable Definition *
//* *
//***********************************************************************
//***********************************************************************
//* *
//* D14 Structure Definition *
//* *
//***********************************************************************
typedef union ADDRESS_REG
{
struct ADDRESS_BITS
{
UC DEVADDR : 7;
UC DEVEN : 1;
}BITS;
UC VALUE;
}ADDRESS_REG;
typedef union USB_MODE
{
struct USB_MODE_BITS
{
UC SOFTCT : 1;
UC PWROFF : 1;
UC WKUPC : 1;
UC GLINTE : 1;
UC SFRESET : 1;
UC GOSUSP : 1;
UC SNDRSU : 1;
UC DISGLBL : 1;
}BITS;
UC VALUE;
}USB_MODE;
typedef union INT_CONFIG
{
struct INT_CONFIG_BITS
{
UC INTPOL : 1;
UC INTLVL : 1;
UC DDBGMODOUT : 2;
UC DDBGMODIN : 2;
UC CDBGMOD : 2;
}BITS;
UC VALUE;
}INT_CONFIG;
typedef union INT_ENABLE
{
struct INT_ENABLE_BITS
{
UC IERST : 1;
UC IESOF : 1;
UC IEPSOF : 1;
UC IESUSP : 1;
UC IEHS_STA : 1;
UC IEDMA : 1;
UC RESERVED3 : 1;
UC IEP0SETUP : 1;
UC RESERVED2 : 1;
UC IEP0RX : 1;
UC IEP0TX : 1;
UC IEP1RX : 1;
UC IEP1TX : 1;
UC IEP2RX : 1;
UC IEP2TX : 1;
UC IEP3RX : 1;
UC IEP3TX : 1;
UC IEP4RX : 1;
UC IEP4TX : 1;
UC IEP5RX : 1;
UC IEP5TX : 1;
UC IEP6RX : 1;
UC IEP6TX : 1;
UC IEP7RX : 1;
UC IEP7TX : 1;
UC RESERVED1 : 6;
}BITS;
UL VALUE;
}INT_ENABLE;
typedef union INTERRUPT_STATUS
{
struct INTERRUPT_STATUS_BITS
{
UC RESET : 1;
UC SOF : 1;
UC PSOF : 1;
UC SUSP : 1;
UC RESUME : 1;
UC HS_STAT : 1;
UC DMA : 1;
UC RESERVED3 : 1;
UC EP0SETUP : 1;
UC RESERVED2 : 1;
UC EP0RX : 1;
UC EP0TX : 1;
UC EP1RX : 1;
UC EP1TX : 1;
UC EP2RX : 1;
UC EP2TX : 1;
UC EP3RX : 1;
UC EP3TX : 1;
UC EP4RX : 1;
UC EP4TX : 1;
UC EP5RX : 1;
UC EP5TX : 1;
UC EP6RX : 1;
UC EP6TX : 1;
UC EP7RX : 1;
UC EP7TX : 1;
UC RESERVED1 : 6;
}BITS;
UL VALUE;
}INTERRUPT_STATUS;
typedef union ENDPT_MAXSIZE
{
struct ENDPT_MAXSIZE_BITS
{
UC FFOSZ7_0 : 8;
UC FFOSZ10_8 : 3;
UC NTRANS : 2;
UC RESERVED2 : 3;
}BITS;
UI VALUE;
}ENDPT_MAXSIZE;
typedef union ENDPT_INDEX
{
struct ENDPT_INDEX_BITS
{
UC DIR : 1;
UC ENDPIDX : 4;
UC EP0SETUP : 1;
UC RESERVED : 2;
}BITS;
UC VALUE;
}ENDPT_INDEX;
typedef union CONTROL
{
struct CONTROL_BITS
{
UC STALL : 1;
UC STATUS : 1;
UC RESERVED2 : 1;
UC VENDP : 1;
UC CLBUF : 1;
UC RESERVED1 : 3;
}BITS;
UC VALUE;
}CONTROL;
typedef union ENDPT_TYPE
{
struct ENDPT_TYPE_BITS
{
UC ENDPTYP : 2;
UC DBLBUF : 1;
UC ENABLE : 1;
UC ZERO_PKT_DIS: 1;
UC RESERVED1 : 3;
UC RESRVED2 : 8;
}BITS;
UI VALUE;
}ENDPT_TYPE;
typedef union ERROR_CODE
{
struct ERROR_CODE_BITS
{
UC RTOK : 1;
UC ERROR : 4;
UC RESERVED: 1;
UC DATA01 : 1;
UC UNREAD : 1;
}BITS;
UC VALUE;
}ERROR_CODE;
typedef union VALIDSHORT
{
struct VALIDSHORT_BITS
{
UC RESERVED : 8;
UC OUT0SH : 1;
UC OUT1SH : 1;
UC OUT2SH : 1;
UC OUT3SH : 1;
UC OUT4SH : 1;
UC OUT5SH : 1;
UC OUT6SH : 1;
UC OUT7SH : 1;
}BITS;
UI VALUE;
}VALIDSHORT;
typedef union FRAME_NO
{
struct FRAME_NO_BITS
{
UC SOFL : 8;
UC SOFH : 3;
UC USOF : 3;
UC RESERVED : 2;
}BITS;
UI VALUE;
}FRAME_NO;
typedef union TESTMODE
{
struct TESTMODE_BITS
{
UC SE0_NAK : 1;
UC JSTATE : 1;
UC KSTATE : 1;
UC PRBS : 1;
UC FORCEFS : 1;
UC LPBK : 1;
UC PHYTEST : 1;
UC FORCEHS : 1;
}BITS;
UC VALUE;
}TESTMODE;
typedef union GDMA_CONFIG
{
struct GDMA_CONFIG_BITS
{
UC WIDTH : 1;
UC RES1 : 1;
UC DMA_MODE : 2;
UC BURST : 3;
UC CNTENA : 1;
}BITS;
UC VALUE;
}GDMA_CONFIG;
typedef union UDMA_CONFIG
{
struct UDMA_CONFIG_BITS
{
UC PIO_MODE : 3;
UC UDMA_MODE : 2;
UC ATA_MODE : 1;
UC IGNORE_IORDY: 1;
UC RES2 : 1;
}BITS;
UC VALUE;
}UDMA_CONFIG;
typedef union DMA_HARDWARE
{
struct DMA_HARDWARE_BITS
{
UC READ_POL : 1;
UC WRITE_POL : 1;
UC DREQ_POL : 1;
UC ACK_POL : 1;
UC MASTER : 1;
UC EOT_POL : 1;
UC ENDIAN : 2;
}BITS;
UC VALUE;
}DMA_HARDWARE;
typedef union DMA_STROBE
{
struct DMA_STROBE_BITS
{
UC DMA_STROBE : 5;
UC RES : 3;
}BITS;
UC VALUE;
}DMA_STROBE;
typedef union DMA_INT
{
struct DMA_INT_BITS
{
UC CMD_AUTO_COMPLETE : 1;
UC INTRQ_PENDING : 1;
UC TASKFILE_READ_COMPLETE : 1;
UC BSY_DRQ_POLL_DONE : 1;
UC START_READ_1F0_RD_FIFO : 1;
UC RD_1F0_FIFO_EMPTY : 1;
UC WR_1F0_FIFO_FULL : 1;
UC WR_1F0_FIFO_EMPTY : 1;
UC DMA_DONE : 1;
UC PENDING_INTRQ : 1;
UC INT_EOT : 1;
UC EXT_EOT : 1;
UC RES1 : 4;
}BITS;
UI VALUE;
}DMA_INT;
typedef union DMA_INT_ENABLE
{
struct DMA_INT_ENABLE_BITS
{
UC CMD_AUTO_COMPLETE : 1;
UC INTRQ_PENDING : 1;
UC TASKFILE_READ_COMPLETE : 1;
UC BSY_DRQ_POLL_DONE : 1;
UC START_READ_1F0_RD_FIFO : 1;
UC RD_1F0_FIFO_EMPTY : 1;
UC WR_1F0_FIFO_FULL : 1;
UC WR_1F0_FIFO_EMPTY : 1;
UC DMA_DONE : 1;
UC RES1 : 7;
}BITS;
UI VALUE;
}DMA_INT_ENABLE;
/*
typedef union DMA_ENDPT
{
struct DMA_ENDPT_BITS
{
UC DMADIR : 1;
UC EDPIDX : 3;
UC NOT_USED : 4;
}BITS;
UC VALUE;
}DMA_ENDPT;
*/
typedef union DMA_STATE_1
{
struct DMA_STATE_1_BITS
{
UC PIO_SEQ_STATE : 3;
UC PIO_CMD_STATE : 5;
}BITS;
UC VALUE;
}DMA_STATE_1;
typedef union DMA_STATE_2
{
struct DMA_STATE_2_BITS
{
UC RES : 8;
}BITS;
UC VALUE;
}DMA_STATE_2;
typedef struct D14_CNTRL_REG
{
ADDRESS_REG D14_ADDRESS;
UC DUMMY_01;
UC DUMMY_02;
UC DUMMY_03;
ENDPT_MAXSIZE D14_ENDPT_MAXPKTSIZE;
UC DUMMY_06;
UC DUMMY_07;
ENDPT_TYPE D14_ENDPT_TYPE;
UC DUMMY_0A;
UC DUMMY_0B;
USB_MODE D14_MODE;
UC DUMMY_0D;
UC DUMMY_0E;
UC DUMMY_0F;
INT_CONFIG D14_INT_CONFIG;
UC DUMMY_11;
UC DUMMY_12;
UC DUMMY_13;
INT_ENABLE D14_INT_ENABLE;
INTERRUPT_STATUS D14_INT;
UC D14_BUFFER_LENGTH_LSB;
UC D14_BUFFER_LENGTH_MSB;
UC DUMMY_1E;
UC DUMMY_1F;
UC D14_DATA_PORT_LSB;
UC D14_DATA_PORT_MSB;
UC DUMMY_22;
UC DUMMY_23;
VALIDSHORT D14_VALIDATE_SHORT;
UC DUMMY_26;
UC DUMMY_27;
CONTROL D14_CONTROL_FUNCTION;
UC DUMMY_29;
UC DUMMY_2A;
UC DUMMY_2B;
UC D14_ENDPT_INDEX;
UC DUMMY_2D;
UC DUMMY_2E;
UC DUMMY_2F;
UC D14_DMA_COMMAND;
UC DUMMY_31;
UC DUMMY_32;
UC DUMMY_33;
UC D14_DMA_TRANSFER_COUNTER_LSB;
UC D14_DMA_TRANSFER_COUNTER_BYTE2;
UC D14_DMA_TRANSFER_COUNTER_BYTE3;
UC D14_DMA_TRANSFER_COUNTER_MSB;
GDMA_CONFIG D14_GDMA_CONFIG;
UDMA_CONFIG D14_UDMA_CONFIG;
UC DUMMY_3A;
UC DUMMY_3B;
DMA_HARDWARE D14_DMA_HARDWARE;
UC DUMMY_3D;
UC DUMMY_3E;
UC DUMMY_3F;
UC D14_DATA_TASKFILE_LSB;
UC DATA_TASKFILE_BYTE2;
UC DATA_TASKFILE_BYTE3;
UC DATA_TASKFILE_MSB;
UC D14_CMD_STATUS_TASKFILE;
UC DUMMY_45;
UC DUMMY_46;
UC DUMMY_47;
UC D14_ERROR_FEATURE_TASKFILE;
UC D14_INTERRUPT_TASKFILE;
UC D14_SECTOR_NUMBER;
UC D14_BYTECOUNT_LSB_TASKFILE;
UC D14_BYTECOUNT_MSB_TASKFILE;
UC D14_DRIVE_SELECT_TASKFILE;
UC D14_ALT_STATUS_DEVCNTRL_TASKFILE;
UC D14_TASKFILE;
DMA_INT D14_DMA_INT;
UC DUMMY_52;
UC DUMMY_53;
DMA_INT_ENABLE D14_DMA_INT_ENABLE;
UC DUMMY_56;
UC DUMMY_57;
UC D14_DMA_ENDPOINT;
UC DUMMY_59;
UC DUMMY_5A;
UC DUMMY_5B;
DMA_STATE_1 D14_DMA_STATE_1;
UC DUMMY_5D;
UC DUMMY_5E;
UC DUMMY_5F;
DMA_STROBE DMA_STROBE_TIMING;
UC DUMMY_61;
UC DUMMY_62;
UC DUMMY_63;
UC UDMA_BYTE_COUNT_LSB;
UC UDMA_BYTE_COUNT_MSB;
UC DUMMY_66;
UC COUNT_1F0;
UC PMU_TRANSFER_COUNT_0;
UC PMU_TRANSFER_COUNT_1;
UC PMU_TRANSFER_COUNT_2;
UC PMU_TRANSFER_COUNT_3;
UC DUMMY_6C;
UC DUMMY_6D;
UC DUMMY_6E;
UC DUMMY_6F;
UC D14_CHIP_ID_LSB;
UC D14_CHIP_ID_MBYTE;
UC D14_CHIP_ID_MSB;
UC DUMMY_73;
FRAME_NO D14_FRAME_NUMBER;
UC DUMMY_76;
UC DUMMY_77;
UI D14_SCRATCH_REGISTER;
UC DUMMY_7A;
UC DUMMY_7B;
UC D14_UNLOCK_DEVICE_LSB;
UC D14_UNLOCK_DEVICE_MSB;
UC DUMMY_7E;
UC DUMMY_7F;
ERROR_CODE D14_ERROR_CODE;
UC DUMMY_81;
UC DUMMY_82;
UC DUMMY_83;
TESTMODE D14_TEST_MODE;
UC DUMMY_85;
UC DUMMY_86;
UC DUMMY_87;
UC DUMMY_88;
}D14_CNTRL_REG;
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