hubmd_next.h

是关于linux2.5.1的完全源码

	bdrkreg_t	pdp_format                :	 2;
        bdrkreg_t       pdp_state                 :      3;
        bdrkreg_t       pdp_priority              :      3;
        bdrkreg_t       pdp_pointer1_a            :      8;
        bdrkreg_t       pdp_reserved_4            :      6;
        bdrkreg_t       pdp_pointer1_b            :      3;
        bdrkreg_t       pdp_reserved_3            :      7;
        bdrkreg_t       pdp_ecc_a                 :      6;
        bdrkreg_t       pdp_locprot               :      1;
        bdrkreg_t       pdp_reserved_2            :      1;
        bdrkreg_t       pdp_crit_word_off         :      3;
        bdrkreg_t       pdp_pointer2_a            :      5;
        bdrkreg_t       pdp_ecc_b                 :      1;
        bdrkreg_t       pdp_reserved_1            :      5;
        bdrkreg_t       pdp_pointer2_b            :      3;
        bdrkreg_t       pdp_reserved              :      7;
};

#else

struct	md_pdir_pointer_fmt { /* exclusive, busy shared/excl, wait, poisoned */
	bdrkreg_t	pdp_reserved		  :	 7;
	bdrkreg_t	pdp_pointer2_b		  :	 3;
	bdrkreg_t	pdp_reserved_1		  :	 5;
	bdrkreg_t	pdp_ecc_b		  :	 1;
	bdrkreg_t	pdp_pointer2_a		  :	 5;
	bdrkreg_t	pdp_crit_word_off	  :	 3;
	bdrkreg_t	pdp_reserved_2		  :	 1;
	bdrkreg_t	pdp_locprot		  :	 1;
	bdrkreg_t	pdp_ecc_a		  :	 6;
	bdrkreg_t	pdp_reserved_3		  :	 7;
	bdrkreg_t	pdp_pointer1_b		  :	 3;
	bdrkreg_t	pdp_reserved_4		  :	 6;
	bdrkreg_t	pdp_pointer1_a		  :	 8;
	bdrkreg_t	pdp_priority		  :	 3;
	bdrkreg_t	pdp_state		  :	 3;
	bdrkreg_t	pdp_format		  :	 2;
};

#endif

#ifdef LITTLE_ENDIAN

struct	md_pdir_fine_fmt { /* shared (fine) */
	bdrkreg_t	pdf_format                :	 2;
        bdrkreg_t       pdf_tag1_a                :      3;
        bdrkreg_t       pdf_tag2_a                :      3;
        bdrkreg_t       pdf_vector1_a             :      8;
        bdrkreg_t       pdf_reserved_1            :      6;
        bdrkreg_t       pdf_tag1_b                :      2;
        bdrkreg_t       pdf_vector1_b             :      8;
        bdrkreg_t       pdf_ecc_a                 :      6;
        bdrkreg_t       pdf_locprot               :      1;
        bdrkreg_t       pdf_tag2valid             :      1;
        bdrkreg_t       pdf_vector2_a             :      8;
        bdrkreg_t       pdf_ecc_b                 :      1;
        bdrkreg_t       pdf_reserved              :      5;
        bdrkreg_t       pdf_tag2_b                :      2;
        bdrkreg_t       pdf_vector2_b             :      8;
};

#else

struct	md_pdir_fine_fmt { /* shared (fine) */
	bdrkreg_t	pdf_vector2_b		  :	 8;
	bdrkreg_t	pdf_tag2_b		  :	 2;
	bdrkreg_t	pdf_reserved		  :	 5;
	bdrkreg_t	pdf_ecc_b		  :	 1;
	bdrkreg_t	pdf_vector2_a		  :	 8;
	bdrkreg_t	pdf_tag2valid		  :	 1;
	bdrkreg_t	pdf_locprot		  :	 1;
	bdrkreg_t	pdf_ecc_a		  :	 6;
	bdrkreg_t	pdf_vector1_b		  :	 8;
	bdrkreg_t	pdf_tag1_b		  :	 2;
	bdrkreg_t	pdf_reserved_1		  :	 6;
	bdrkreg_t	pdf_vector1_a		  :	 8;
	bdrkreg_t	pdf_tag2_a		  :	 3;
	bdrkreg_t	pdf_tag1_a		  :	 3;
	bdrkreg_t	pdf_format		  :	 2;
};

#endif

#ifdef LITTLE_ENDIAN

struct	md_pdir_sparse_fmt { /* shared (sparse) */
	bdrkreg_t	pds_format                :	 2;
        bdrkreg_t       pds_column_a              :      6;
        bdrkreg_t       pds_row_a                 :      8;
        bdrkreg_t       pds_column_b              :     16;
        bdrkreg_t       pds_ecc_a                 :      6;
        bdrkreg_t       pds_locprot               :      1;
        bdrkreg_t       pds_reserved_1            :      1;
        bdrkreg_t       pds_row_b                 :      8;
        bdrkreg_t       pds_ecc_b                 :      1;
        bdrkreg_t       pds_column_c              :     10;
        bdrkreg_t       pds_reserved              :      5;
};

#else

struct	md_pdir_sparse_fmt { /* shared (sparse) */
	bdrkreg_t	pds_reserved		  :	 5;
	bdrkreg_t	pds_column_c		  :	10;
	bdrkreg_t	pds_ecc_b		  :	 1;
	bdrkreg_t	pds_row_b		  :	 8;
	bdrkreg_t	pds_reserved_1		  :	 1;
	bdrkreg_t	pds_locprot		  :	 1;
	bdrkreg_t	pds_ecc_a		  :	 6;
	bdrkreg_t	pds_column_b		  :	16;
	bdrkreg_t	pds_row_a		  :	 8;
	bdrkreg_t	pds_column_a		  :	 6;
	bdrkreg_t	pds_format		  :	 2;
};

#endif

typedef union md_pdir {
	/* The 64 bits of premium directory */
	uint64_t	pd_val;
	struct	md_pdir_pointer_fmt	pdp_fmt;
	struct	md_pdir_fine_fmt	pdf_fmt;
	struct	md_pdir_sparse_fmt	pds_fmt;
} md_pdir_t;

#endif /* __ASSEMBLY__ */


/**********************************************************************

 The defines for backdoor directory and backdoor ECC.

***********************************************************************/

/* Directory formats, for each format's "format" field */

#define MD_FORMAT_UNOWNED	(UINT64_CAST 0x0)	/* 00 */
#define MD_FORMAT_POINTER	(UINT64_CAST 0x1)	/* 01 */
#define MD_FORMAT_SHFINE	(UINT64_CAST 0x2)	/* 10 */
#define MD_FORMAT_SHCOARSE	(UINT64_CAST 0x3)	/* 11 */
  /* Shared coarse (standard) and shared sparse (premium) both use fmt 0x3 */


/*
 * Cacheline state values.
 *
 * These are really *software* notions of the "state" of a cacheline; but the
 * actual values have been carefully chosen to align with some hardware values!
 * The MD_FMT_ST_TO_STATE macro is used to convert from hardware format/state
 * pairs in the directory entried into one of these cacheline state values.
 */

#define MD_DIR_EXCLUSIVE	(UINT64_CAST 0x0)	/* ptr format, hw-defined */
#define MD_DIR_UNOWNED		(UINT64_CAST 0x1)	/* format=0 */
#define MD_DIR_SHARED		(UINT64_CAST 0x2)	/* format=2,3 */
#define MD_DIR_BUSY_SHARED	(UINT64_CAST 0x4)	/* ptr format, hw-defined */
#define MD_DIR_BUSY_EXCL	(UINT64_CAST 0x5)	/* ptr format, hw-defined */
#define MD_DIR_WAIT		(UINT64_CAST 0x6)	/* ptr format, hw-defined */
#define MD_DIR_POISONED		(UINT64_CAST 0x7)	/* ptr format, hw-defined */

#ifndef __ASSEMBLY__

/* Convert format and state fields into a single "cacheline state" value, defined above */

#define MD_FMT_ST_TO_STATE(fmt, state) \
  ((fmt) == MD_FORMAT_POINTER ? (state) : \
   (fmt) == MD_FORMAT_UNOWNED ? MD_DIR_UNOWNED : \
   MD_DIR_SHARED)
#define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x))

#endif /* __ASSEMBLY__ */



/* Directory field shifts and masks */

/* Standard */

#define MD_SDIR_FORMAT_SHFT	0			/* All formats */
#define MD_SDIR_FORMAT_MASK	(0x3 << 0)
#define MD_SDIR_STATE_SHFT	2			/* Pointer fmt. only */
#define MD_SDIR_STATE_MASK	(0x7 << 2)

/* Premium */

#define MD_PDIR_FORMAT_SHFT	0			/* All formats */
#define MD_PDIR_FORMAT_MASK	(0x3 << 0)
#define MD_PDIR_STATE_SHFT	2			/* Pointer fmt. only */
#define MD_PDIR_STATE_MASK	(0x7 << 2)

/* Generic */

#define MD_FORMAT_SHFT	0				/* All formats */
#define MD_FORMAT_MASK	(0x3 << 0)
#define MD_STATE_SHFT	2				/* Pointer fmt. only */
#define MD_STATE_MASK	(0x7 << 2)


/* Special shifts to reconstruct fields from the _a and _b parts */

/* Standard:  only shared coarse has split fields */

#define MD_SDC_VECTORB_SHFT	8	/* eg: sdc_vector_a is 8 bits */

/* Premium:  pointer, shared fine, shared sparse */

#define MD_PDP_POINTER1A_MASK	0xFF
#define MD_PDP_POINTER1B_SHFT	8
#define MD_PDP_POINTER2B_SHFT	5
#define MD_PDP_ECCB_SHFT	6

#define MD_PDF_VECTOR1B_SHFT	8
#define MD_PDF_VECTOR2B_SHFT	8
#define MD_PDF_TAG1B_SHFT	3
#define MD_PDF_TAG2B_SHFT	3
#define MD_PDF_ECC_SHFT		6

#define MD_PDS_ROWB_SHFT	8
#define MD_PDS_COLUMNB_SHFT	6
#define MD_PDS_COLUMNC_SHFT	(MD_PDS_COLUMNB_SHFT + 16)
#define MD_PDS_ECC_SHFT		6



/*
 * Directory/protection/counter initialization values, premium and standard
 */

#define MD_PDIR_INIT		0
#define MD_PDIR_INIT_CNT	0
#define MD_PDIR_INIT_PROT	0

#define MD_SDIR_INIT		0
#define MD_SDIR_INIT_CNT	0
#define MD_SDIR_INIT_PROT	0

#define MD_PDIR_MASK            0xffffffffffffffff
#define MD_SDIR_MASK            0xffffffff

/* When premium mode is on for probing but standard directory memory
   is installed, the valid directory bits depend on the phys. bank */
#define MD_PDIR_PROBE_MASK(pb)  0xffffffffffffffff
#define MD_SDIR_PROBE_MASK(pb)  (0xffff0000ffff << ((pb) ? 16 : 0))


/*
 * Misc. field extractions and conversions
 */

/* Convert an MD pointer (or message source, supplemental fields) */

#define MD_PTR_NODE(x)		((x) >> MD_PTR_NODE_SHFT)
#define MD_PTR_DEVICE(x)	((x) & MD_PTR_DEVICE_MASK)
#define MD_PTR_SLICE(x)		(((x) & MD_PTR_SUBNODE0_MASK) | \
				 ((x) & MD_PTR_SUBNODE1_MASK) >> 1)
#define MD_PTR_OWNER_CPU(x)	(! ((x) & 2))
#define MD_PTR_OWNER_IO(x)	((x) & 2)

/* Extract format and raw state from a directory entry */

#define MD_DIR_FORMAT(x)	((x) >> MD_SDIR_FORMAT_SHFT & \
				 MD_SDIR_FORMAT_MASK >> MD_SDIR_FORMAT_SHFT)
#define MD_DIR_STVAL(x)		((x) >> MD_SDIR_STATE_SHFT & \
				 MD_SDIR_STATE_MASK >> MD_SDIR_STATE_SHFT)

/* Mask & Shift to get HSPEC_ADDR from MD DIR_ERROR register */
#define ERROR_ADDR_SHFT         3
#define ERROR_HSPEC_SHFT        3
#define DIR_ERR_HSPEC_MASK      0x1fffffff8

/*
 *  DIR_ERR* and MEM_ERR* defines are used to avoid ugly
 *  #ifdefs for SN0 and SN1 in memerror.c code.  See SN0/hubmd.h
 *  for corresponding SN0 definitions.
 */
#define md_dir_error_t  md_dir_error_u_t
#define md_mem_error_t  md_mem_error_u_t
#define derr_reg        md_dir_error_regval
#define merr_reg        md_mem_error_regval

#define DIR_ERR_UCE_VALID       dir_err.md_dir_error_fld_s.de_uce_valid
#define DIR_ERR_AE_VALID        dir_err.md_dir_error_fld_s.de_ae_valid
#define DIR_ERR_BAD_SYN         dir_err.md_dir_error_fld_s.de_bad_syn
#define DIR_ERR_CE_OVERRUN      dir_err.md_dir_error_fld_s.de_ce_overrun
#define MEM_ERR_ADDRESS         mem_err.md_mem_error_fld_s.me_address
        /* BRINGUP Can the overrun bit be set without the valid bit? */
#define MEM_ERR_CE_OVERRUN      (mem_err.md_mem_error_fld_s.me_read_ce >> 1)
#define MEM_ERR_BAD_SYN         mem_err.md_mem_error_fld_s.me_bad_syn
#define MEM_ERR_UCE_VALID       (mem_err.md_mem_error_fld_s.me_read_uce & 1)



/*********************************************************************

 We have the shift and masks of various fields defined below.

 *********************************************************************/

/* MD_REFRESH_CONTROL fields */

#define MRC_ENABLE_SHFT         63
#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
#define MRC_ENABLE              (UINT64_CAST 1 << 63)
#define MRC_COUNTER_SHFT        12
#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
#define MRC_CNT_THRESH_MASK     0xfff
#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x800)

/* MD_DIR_CONFIG fields */

#define MDC_DIR_PREMIUM		(UINT64_CAST 1 << 0)
#define MDC_IGNORE_ECC_SHFT      1
#define MDC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 1)

/* MD_MEMORY_CONFIG fields */

#define MMC_RP_CONFIG_SHFT	61
#define MMC_RP_CONFIG_MASK	(UINT64_CAST 1 << 61)
#define MMC_RCD_CONFIG_SHFT	60
#define MMC_RCD_CONFIG_MASK	(UINT64_CAST 1 << 60)
#define MMC_MB_NEG_EDGE_SHFT	56
#define MMC_MB_NEG_EDGE_MASK	(UINT64_CAST 0x7 << 56)
#define MMC_SAMPLE_TIME_SHFT	52
#define MMC_SAMPLE_TIME_MASK	(UINT64_CAST 0x3 << 52)
#define MMC_DELAY_MUX_SEL_SHFT	50
#define MMC_DELAY_MUX_SEL_MASK	(UINT64_CAST 0x3 << 50)
#define MMC_PHASE_DELAY_SHFT	49
#define MMC_PHASE_DELAY_MASK	(UINT64_CAST 1 << 49)
#define MMC_DB_NEG_EDGE_SHFT	48
#define MMC_DB_NEG_EDGE_MASK	(UINT64_CAST 1 << 48)
#define MMC_CPU_PROT_IGNORE_SHFT	 47
#define MMC_CPU_PROT_IGNORE_MASK	(UINT64_CAST 1 << 47)
#define MMC_IO_PROT_IGNORE_SHFT 46
#define MMC_IO_PROT_IGNORE_MASK	(UINT64_CAST 1 << 46)
#define MMC_IO_PROT_EN_SHFT	45
#define MMC_IO_PROT_EN_MASK	(UINT64_CAST 1 << 45)
#define MMC_CC_ENABLE_SHFT	44
#define MMC_CC_ENABLE_MASK	(UINT64_CAST 1 << 44)
#define MMC_DIMM0_SEL_SHFT	32
#define MMC_DIMM0_SEL_MASK     (UINT64_CAST 0x3 << 32)
#define MMC_DIMM_SIZE_SHFT(_dimm)    ((_dimm << 3) + 4)
#define MMC_DIMM_SIZE_MASK(_dimm)    (UINT64_CAST 0xf << MMC_DIMM_SIZE_SHFT(_dimm))
#define MMC_DIMM_WIDTH_SHFT(_dimm)    ((_dimm << 3) + 3)
#define MMC_DIMM_WIDTH_MASK(_dimm)    (UINT64_CAST 0x1 << MMC_DIMM_WIDTH_SHFT(_dimm))
#define MMC_DIMM_BANKS_SHFT(_dimm)    (_dimm << 3)
#define MMC_DIMM_BANKS_MASK(_dimm)    (UINT64_CAST 0x3 << MMC_DIMM_BANKS_SHFT(_dimm))
#define MMC_BANK_ALL_MASK	0xffffffffLL
/* Default values for write-only bits in MD_MEMORY_CONFIG */
#define MMC_DEFAULT_BITS	(UINT64_CAST 0x7 << MMC_MB_NEG_EDGE_SHFT)

/* MD_MB_ECC_CONFIG fields */

#define MEC_IGNORE_ECC		(UINT64_CAST 0x1 << 0)

/* MD_BIST_DATA fields */

#define MBD_BIST_WRITE		(UINT64_CAST 1 << 7)
#define MBD_BIST_CYCLE		(UINT64_CAST 1 << 6)
#define MBD_BIST_BYTE		(UINT64_CAST 1 << 5)
#define MBD_BIST_NIBBLE		(UINT64_CAST 1 << 4)
#define MBD_BIST_DATA_MASK	0xf

/* MD_BIST_CTL fields */

#define MBC_DIMM_SHFT		5
#define MBC_DIMM_MASK		(UINT64_CAST 0x3 << 5)
#define MBC_BANK_SHFT		4
#define MBC_BANK_MASK		(UINT64_CAST 0x1 << 4)
#define MBC_BIST_RESET		(UINT64_CAST 0x1 << 2)
#define MBC_BIST_STOP		(UINT64_CAST 0x1 << 1)
#define MBC_BIST_START		(UINT64_CAST 0x1 << 0)

#define MBC_GO(dimm, bank) \
    (((dimm) << MBC_DIMM_SHFT) & MBC_DIMM_MASK | \
     ((bank) << MBC_BANK_SHFT) & MBC_BANK_MASK | \
     MBC_BIST_START)

/* MD_BIST_STATUS fields */

#define MBS_BIST_DONE		(UINT64_CAST 0X1 << 1)
#define MBS_BIST_PASSED		(UINT64_CAST 0X1 << 0)

/* MD_JUNK_BUS_TIMING fields */

#define MJT_SYNERGY_ENABLE_SHFT	40
#define MJT_SYNERGY_ENABLE_MASK	(UINT64_CAST 0Xff << MJT_SYNERGY_ENABLE_SHFT)
#define MJT_SYNERGY_SETUP_SHFT	32
#define MJT_SYNERGY_SETUP_MASK	(UINT64_CAST 0Xff << MJT_SYNERGY_SETUP_SHFT)
#define MJT_UART_ENABLE_SHFT	24
#define MJT_UART_ENABLE_MASK	(UINT64_CAST 0Xff << MJT_UART_ENABLE_SHFT)
#define MJT_UART_SETUP_SHFT	16
#define MJT_UART_SETUP_MASK	(UINT64_CAST 0Xff << MJT_UART_SETUP_SHFT)
#define MJT_FPROM_ENABLE_SHFT	8
#define MJT_FPROM_ENABLE_MASK	(UINT64_CAST 0Xff << MJT_FPROM_ENABLE_SHFT)
#define MJT_FPROM_SETUP_SHFT	0
#define MJT_FPROM_SETUP_MASK	(UINT64_CAST 0Xff << MJT_FPROM_SETUP_SHFT)

#define MEM_ERROR_VALID_CE      1


/* MD_FANDOP_CAC_STAT0, MD_FANDOP_CAC_STAT1 addr field shift */

#define MFC_ADDR_SHFT		6

#endif  /* _ASM_IA64_SN_SN1_HUBMD_NEXT_H */