e100.h

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/*******************************************************************************

This software program is available to you under a choice of one of two 
licenses. You may choose to be licensed under either the GNU General Public 
License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
or the Intel BSD + Patent License, the text of which follows:

Recipient has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled Linux Base Driver for the 
Intel(R) PRO/100 Family of Adapters (e100) (the "Software") being provided 
by Intel Corporation. The following definitions apply to this license:

"Licensed Patents" means patent claims licensable by Intel Corporation which 
are necessarily infringed by the use of sale of the Software alone or when 
combined with the operating system referred to below.

"Recipient" means the party to whom Intel delivers this Software.

"Licensee" means Recipient and those third parties that receive a license to 
any operating system available under the GNU General Public License 2.0 or 
later.

Copyright (c) 1999 - 2002 Intel Corporation.
All rights reserved.

The license is provided to Recipient and Recipient's Licensees under the 
following terms.

Redistribution and use in source and binary forms of the Software, with or 
without modification, are permitted provided that the following conditions 
are met:

Redistributions of source code of the Software may retain the above 
copyright notice, this list of conditions and the following disclaimer.

Redistributions in binary form of the Software may reproduce the above 
copyright notice, this list of conditions and the following disclaimer in 
the documentation and/or materials provided with the distribution.

Neither the name of Intel Corporation nor the names of its contributors 
shall be used to endorse or promote products derived from this Software 
without specific prior written permission.

Intel hereby grants Recipient and Licensees a non-exclusive, worldwide, 
royalty-free patent license under Licensed Patents to make, use, sell, offer 
to sell, import and otherwise transfer the Software, if any, in source code 
and object code form. This license shall include changes to the Software 
that are error corrections or other minor changes to the Software that do 
not add functionality or features when the Software is incorporated in any 
version of an operating system that has been distributed under the GNU 
General Public License 2.0 or later. This patent license shall apply to the 
combination of the Software and any operating system licensed under the GNU 
General Public License 2.0 or later if, at the time Intel provides the 
Software to Recipient, such addition of the Software to the then publicly 
available versions of such operating systems available under the GNU General 
Public License 2.0 or later (whether in gold, beta or alpha form) causes 
such combination to be covered by the Licensed Patents. The patent license 
shall not apply to any other combinations which include the Software. NO 
hardware per se is licensed hereunder.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
IMPLIED WARRANTIES OF MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR IT CONTRIBUTORS BE LIABLE FOR ANY 
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(INCLUDING, BUT NOT LIMITED, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
ANY LOSS OF USE; DATA, OR PROFITS; OR BUSINESS INTERUPTION) HOWEVER CAUSED 
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR 
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/

#ifndef _E100_INC_
#define _E100_INC_

#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/version.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <asm/processor.h>
#ifdef SIOCETHTOOL
#include <linux/ethtool.h>
#include <linux/inetdevice.h>
#endif

#include <linux/if.h>
#include <asm/uaccess.h>
#include <linux/proc_fs.h>
#include <linux/ip.h>

/*
 *  Configure parameters for buffers per controller.
 *  If the machine this is being used on is a faster machine (i.e. > 150MHz)
 *  and running on a 10MBS network then more queueing of data occurs. This
 *  may indicate the some of the numbers below should be adjusted.  Here are
 *  some typical numbers:
 *                             MAX_TCB 64
 *                             MAX_RFD 64
 *  The default numbers give work well on most systems tests so no real
 *  adjustments really need to take place.  Also, if the machine is connected
 *  to a 100MBS network the numbers described above can be lowered from the
 *  defaults as considerably less data will be queued.
 */

#define TX_FRAME_CNT   8	/* consecutive transmit frames per interrupt */
/* TX_FRAME_CNT must be less than MAX_TCB    */

#define E100_DEFAULT_TCB   64
#define E100_MIN_TCB       2*TX_FRAME_CNT + 3	/* make room for at least 2 interrupts */
#define E100_MAX_TCB       1024

#define E100_DEFAULT_RFD   64
#define E100_MIN_RFD       8
#define E100_MAX_RFD       1024

#define E100_DEFAULT_XSUM         true
#define E100_DEFAULT_BER          ZLOCK_MAX_ERRORS
#define E100_DEFAULT_SPEED_DUPLEX 0
#define E100_DEFAULT_FC           0
#define E100_DEFAULT_IFS          true
#define E100_DEFAULT_UCODE        true

#define TX_THRSHLD     8

/* IFS parameters */
#define MIN_NUMBER_OF_TRANSMITS_100 1000
#define MIN_NUMBER_OF_TRANSMITS_10  100

#define E100_MAX_NIC 16

#define E100_MAX_SCB_WAIT	100	/* Max udelays in wait_scb */
#define E100_MAX_CU_IDLE_WAIT	50	/* Max udelays in wait_cus_idle */

/* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled.
 * In some situations, such as the TCP windowing algorithm, it may be
 * better to limit the growth of the bundle size than let it go as
 * high as it can, because that could cause too much added latency.
 * The default is six, because this is the number of packets in the
 * default TCP window size.  A value of 1 would make CPUSaver indicate
 * an interrupt for every frame received.  If you do not want to put
 * a limit on the bundle size, set this value to xFFFF.
 */
#define E100_DEFAULT_CPUSAVER_BUNDLE_MAX	6
#define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY	0x600
#define E100_DEFAULT_BUNDLE_SMALL_FR		false
#define E100_DEFAULT_RX_CONGESTION_CONTROL	true

/* end of configurables */

/* ====================================================================== */
/*                                hw                                      */
/* ====================================================================== */

/* timeout for command completion */
#define E100_CMD_WAIT   100	/* iterations */

struct driver_stats {
	struct net_device_stats net_stats;

	unsigned long tx_late_col;
	unsigned long tx_ok_defrd;
	unsigned long tx_one_retry;
	unsigned long tx_mt_one_retry;
	unsigned long rcv_cdt_frames;
	unsigned long xmt_fc_pkts;
	unsigned long rcv_fc_pkts;
	unsigned long rcv_fc_unsupported;
	unsigned long xmt_tco_pkts;
	unsigned long rcv_tco_pkts;
	unsigned long rx_intr_pkts;
	unsigned long rx_tasklet_pkts;
	unsigned long poll_intr_switch;
};

/* TODO: kill me when we can do C99 */
#define false		(0)
#define true		(1)

/* Changed for 82558 and 82559 enhancements */
/* defines for 82558/9 flow control CSR values */
#define DFLT_FC_THLD       0x00	/* Rx FIFO threshold of 0.5KB free  */
#define DFLT_FC_CMD        0x00	/* FC Command in CSR */

/* ====================================================================== */
/*                              equates                                   */
/* ====================================================================== */

/*
 * These are general purpose defines 
 */

/* Bit Mask definitions */
#define BIT_0       0x0001
#define BIT_1       0x0002
#define BIT_2       0x0004
#define BIT_3       0x0008
#define BIT_4       0x0010
#define BIT_5       0x0020
#define BIT_6       0x0040
#define BIT_7       0x0080
#define BIT_8       0x0100
#define BIT_9       0x0200
#define BIT_10      0x0400
#define BIT_11      0x0800
#define BIT_12      0x1000
#define BIT_13      0x2000
#define BIT_14      0x4000
#define BIT_15      0x8000
#define BIT_28      0x10000000

#define BIT_0_2     0x0007
#define BIT_0_3     0x000F
#define BIT_0_4     0x001F
#define BIT_0_5     0x003F
#define BIT_0_6     0x007F
#define BIT_0_7     0x00FF
#define BIT_0_8     0x01FF
#define BIT_0_13    0x3FFF
#define BIT_0_15    0xFFFF
#define BIT_1_2     0x0006
#define BIT_1_3     0x000E
#define BIT_2_5     0x003C
#define BIT_3_4     0x0018
#define BIT_4_5     0x0030
#define BIT_4_6     0x0070
#define BIT_4_7     0x00F0
#define BIT_5_7     0x00E0
#define BIT_5_12    0x1FE0
#define BIT_5_15    0xFFE0
#define BIT_6_7     0x00c0
#define BIT_7_11    0x0F80
#define BIT_8_10    0x0700
#define BIT_9_13    0x3E00
#define BIT_12_15   0xF000
#define BIT_8_15    0xFF00

#define BIT_16_20   0x001F0000
#define BIT_21_25   0x03E00000
#define BIT_26_27   0x0C000000

/* Transmit Threshold related constants */
#define DEFAULT_TX_PER_UNDERRUN         20000

#define MAX_MULTICAST_ADDRS             64
#define MAX_FILTER                      16

#define FULL_DUPLEX      2
#define HALF_DUPLEX      1

/*
 * These defines are specific to the 82557 
 */

/* E100 PORT functions -- lower 4 bits */
#define PORT_SOFTWARE_RESET         0
#define PORT_SELFTEST               1
#define PORT_SELECTIVE_RESET        2
#define PORT_DUMP                   3

/* SCB Status Word bit definitions */
/* Interrupt status/ack fields */
/* ER and FCP interrupts for 82558 masks  */
#define SCB_STATUS_ACK_MASK        BIT_8_15	/* Status Mask */
#define SCB_STATUS_ACK_CX          BIT_15	/* CU Completed Action Cmd */
#define SCB_STATUS_ACK_FR          BIT_14	/* RU Received A Frame */
#define SCB_STATUS_ACK_CNA         BIT_13	/* CU Became Inactive (IDLE) */
#define SCB_STATUS_ACK_RNR         BIT_12	/* RU Became Not Ready */
#define SCB_STATUS_ACK_MDI         BIT_11	/* MDI read or write done */
#define SCB_STATUS_ACK_SWI         BIT_10	/* S/W generated interrupt */
#define SCB_STATUS_ACK_ER          BIT_9	/* Early Receive */
#define SCB_STATUS_ACK_FCP         BIT_8	/* Flow Control Pause */

/*- CUS Fields */
#define SCB_CUS_MASK            (BIT_6 | BIT_7)	/* CUS 2-bit Mask */
#define SCB_CUS_IDLE            0	/* CU Idle */
#define SCB_CUS_SUSPEND         BIT_6	/* CU Suspended */
#define SCB_CUS_ACTIVE          BIT_7	/* CU Active */

/*- RUS Fields */
#define SCB_RUS_IDLE            0	/* RU Idle */
#define SCB_RUS_MASK            BIT_2_5	/* RUS 3-bit Mask */
#define SCB_RUS_SUSPEND         BIT_2	/* RU Suspended */
#define SCB_RUS_NO_RESOURCES    BIT_3	/* RU Out Of Resources */
#define SCB_RUS_READY           BIT_4	/* RU Ready */
#define SCB_RUS_SUSP_NO_RBDS    (BIT_2 | BIT_5)	/* RU No More RBDs */
#define SCB_RUS_NO_RBDS         (BIT_3 | BIT_5)	/* RU No More RBDs */
#define SCB_RUS_READY_NO_RBDS   (BIT_4 | BIT_5)	/* RU Ready, No RBDs */

/* SCB Command Word bit definitions */
/*- CUC fields */
/* Changing mask to 4 bits */
#define SCB_CUC_MASK            BIT_4_7	/* CUC 4-bit Mask */
#define SCB_CUC_NOOP            0
#define SCB_CUC_START           BIT_4	/* CU Start */
#define SCB_CUC_RESUME          BIT_5	/* CU Resume */
/* Changed for 82558 enhancements */
#define SCB_CUC_STATIC_RESUME   (BIT_5 | BIT_7)	/* 82558/9 Static Resume */
#define SCB_CUC_DUMP_ADDR       BIT_6	/* CU Dump Counters Address */
#define SCB_CUC_DUMP_STAT       (BIT_4 | BIT_6)	/* CU Dump stat. counters */
#define SCB_CUC_LOAD_BASE       (BIT_5 | BIT_6)	/* Load the CU base */
/* Below was defined as BIT_4_7 */
#define SCB_CUC_DUMP_RST_STAT   BIT_4_6	/* CU Dump & reset statistics cntrs */

/*- RUC fields */
#define SCB_RUC_MASK            BIT_0_2	/* RUC 3-bit Mask */
#define SCB_RUC_START           BIT_0	/* RU Start */
#define SCB_RUC_RESUME          BIT_1	/* RU Resume */
#define SCB_RUC_ABORT           BIT_2	/* RU Abort */
#define SCB_RUC_LOAD_HDS        (BIT_0 | BIT_2)	/* Load RFD Header Data Size */
#define SCB_RUC_LOAD_BASE       (BIT_1 | BIT_2)	/* Load the RU base */
#define SCB_RUC_RBD_RESUME      BIT_0_2	/* RBD resume */

/* Interrupt fields (assuming byte addressing) */
#define SCB_INT_MASK            BIT_0	/* Mask interrupts */
#define SCB_SOFT_INT            BIT_1	/* Generate a S/W interrupt */
/*  Specific Interrupt Mask Bits (upper byte of SCB Command word) */
#define SCB_FCP_INT_MASK        BIT_2	/* Flow Control Pause */
#define SCB_ER_INT_MASK         BIT_3	/* Early Receive */
#define SCB_RNR_INT_MASK        BIT_4	/* RU Not Ready */
#define SCB_CNA_INT_MASK        BIT_5	/* CU Not Active */
#define SCB_FR_INT_MASK         BIT_6	/* Frame Received */
#define SCB_CX_INT_MASK         BIT_7	/* CU eXecution w/ I-bit done */
#define SCB_BACHELOR_INT_MASK   BIT_2_7	/* 82558 interrupt mask bits */

#define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7

/* EEPROM bit definitions */
/*- EEPROM control register bits */
#define EN_TRNF          0x10	/* Enable turnoff */
#define EEDO             0x08	/* EEPROM data out */
#define EEDI             0x04	/* EEPROM data in (set for writing data) */
#define EECS             0x02	/* EEPROM chip select (1=hi, 0=lo) */
#define EESK             0x01	/* EEPROM shift clock (1=hi, 0=lo) */

/*- EEPROM opcodes */
#define EEPROM_READ_OPCODE          06
#define EEPROM_WRITE_OPCODE         05
#define EEPROM_ERASE_OPCODE         07
#define EEPROM_EWEN_OPCODE          19	/* Erase/write enable */