📄 ramlib_xil.vhd
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-- Generate the write enables
WE_GEN: for i in (2**(addr_bits-12))-1 downto 0 generate
begin
process (wr_en, wr_addr)
begin
if integer_to_slv(i, addr_bits-12) = wr_addr(addr_bits-1 downto 12) and wr_en='1' then
write_enable(i) <= '1';
else
write_enable(i) <= '0';
end if;
end process;
end generate WE_GEN;
------------------------------------
-- Register the upper read address bits
process (reset, rd_clk)
begin
if reset='1' then
rd_addr_reg <= (others=>'0');
elsif rd_clk'event and rd_clk='1' then
rd_addr_reg <= rd_addr (addr_bits-1 downto 12);
end if;
end process;
------------------------------------
-- Mux the data outputs
rd_data <= d_port2_dout(slv_to_integer(rd_addr_reg));
end arch_ram_x1_dp_block;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;
entity ram_dp_block is
generic (addr_bits :integer;
data_bits :integer;
register_out_flag :integer := 0;
block_type :integer := 0);
port (reset :in std_logic;
wr_clk :in std_logic;
wr_en :in std_logic;
wr_addr :in std_logic_vector (addr_bits-1 downto 0);
wr_data :in std_logic_vector (data_bits-1 downto 0);
rd_clk :in std_logic;
rd_addr :in std_logic_vector (addr_bits-1 downto 0);
rd_data :out std_logic_vector (data_bits-1 downto 0)
);
end ram_dp_block;
architecture arch_ram_dp_block of ram_dp_block is
signal always_one :std_logic;
signal always_zero :std_logic;
component RAMB4_S1_S1
port (WEA, ENA, RSTA, CLKA :in std_logic;
ADDRA :in std_logic_vector (11 downto 0);
DIA :in std_logic;
DOA :out std_logic;
WEB, ENB, RSTB, CLKB :in std_logic;
ADDRB :in std_logic_vector (11 downto 0);
DIB :in std_logic;
DOB :out std_logic
);
end component;
component RAMB4_S2_S2
port (WEA, ENA, RSTA, CLKA :in std_logic;
ADDRA :in std_logic_vector (10 downto 0);
DIA :in std_logic_vector (1 downto 0);
DOA :out std_logic_vector (1 downto 0);
WEB, ENB, RSTB, CLKB :in std_logic;
ADDRB :in std_logic_vector (10 downto 0);
DIB :in std_logic_vector (1 downto 0);
DOB :out std_logic_vector (1 downto 0)
);
end component;
component RAMB4_S4_S4
port (WEA, ENA, RSTA, CLKA :in std_logic;
ADDRA :in std_logic_vector (9 downto 0);
DIA :in std_logic_vector (3 downto 0);
DOA :out std_logic_vector (3 downto 0);
WEB, ENB, RSTB, CLKB :in std_logic;
ADDRB :in std_logic_vector (9 downto 0);
DIB :in std_logic_vector (3 downto 0);
DOB :out std_logic_vector (3 downto 0)
);
end component;
component RAMB4_S8_S8
port (WEA, ENA, RSTA, CLKA :in std_logic;
ADDRA :in std_logic_vector (8 downto 0);
DIA :in std_logic_vector (7 downto 0);
DOA :out std_logic_vector (7 downto 0);
WEB, ENB, RSTB, CLKB :in std_logic;
ADDRB :in std_logic_vector (8 downto 0);
DIB :in std_logic_vector (7 downto 0);
DOB :out std_logic_vector (7 downto 0)
);
end component;
component RAMB4_S16_S16
port (WEA, ENA, RSTA, CLKA :in std_logic;
ADDRA :in std_logic_vector (7 downto 0);
DIA :in std_logic_vector (15 downto 0);
DOA :out std_logic_vector (15 downto 0);
WEB, ENB, RSTB, CLKB :in std_logic;
ADDRB :in std_logic_vector (7 downto 0);
DIB :in std_logic_vector (15 downto 0);
DOB :out std_logic_vector (15 downto 0)
);
end component;
signal wr_dummy :std_logic_vector (data_bits-1 downto 0);
signal rd_dummy :std_logic_vector (data_bits-1 downto 0);
signal wr_dummy2 :std_logic_vector (15 downto 0);
signal rd_dummy2 :std_logic_vector (15 downto 0);
signal last_in :std_logic_vector (15 downto 0);
signal last_out :std_logic_vector (15 downto 0);
signal wr_addr2 :std_logic_vector (7 downto 0);
signal rd_addr2 :std_logic_vector (7 downto 0);
begin
always_one <= '1';
always_zero <= '0';
rd_dummy <= (others=>'0');
rd_dummy2 <= (others=>'0');
--------------------------------------------
-- Needs smaller than a 256xN RAM, use 256x16's anyway
--------------------------------------------
ADDRMIN: if addr_bits<8 generate
begin
CLEARMIN_ADDR: for i in rd_addr2'high downto addr_bits generate
begin
rd_addr2(i) <= '0';
wr_addr2(i) <= '0';
end generate CLEARMIN_ADDR;
rd_addr2(addr_bits-1 downto 0) <= rd_addr;
wr_addr2(addr_bits-1 downto 0) <= wr_addr;
RAMMIN: for i in 0 to (data_bits/16)-1 generate
begin
RAMX16: component RAMB4_S16_S16 port map
(wr_en , always_one, reset, wr_clk, wr_addr2, wr_data(16*i+15 downto 16*i), wr_dummy(16*i+15 downto 16*i),
always_zero, always_one, reset, rd_clk, rd_addr2, rd_dummy(16*i+15 downto 16*i), rd_data(16*i+15 downto 16*i));
end generate RAMMIN;
RAMMINA: if (data_bits mod 16) /= 0 generate
begin
CLEARMIN: for i in last_in'high downto (data_bits mod 16) generate
begin
last_in(i) <= '0';
end generate CLEARMIN;
last_in((data_bits mod 16)-1 downto 0) <= wr_data(data_bits-1 downto data_bits-(data_bits mod 16));
rd_data(data_bits-1 downto data_bits-(data_bits mod 16)) <= last_out((data_bits mod 16)-1 downto 0);
RAMX16A: component RAMB4_S16_S16 port map
(wr_en , always_one, reset, wr_clk, wr_addr2, last_in(15 downto 0), wr_dummy2(15 downto 0),
always_zero, always_one, reset, rd_clk, rd_addr2, rd_dummy2(15 downto 0), last_out(15 downto 0));
end generate RAMMINA;
end generate ADDRMIN;
--------------------------------------------
-- Use 256x16 RAM's
--------------------------------------------
ADDR8: if addr_bits=8 generate
begin
RAM8: for i in 0 to (data_bits/16)-1 generate
begin
RAMX16: component RAMB4_S16_S16 port map
(wr_en , always_one, reset, wr_clk, wr_addr, wr_data(16*i+15 downto 16*i), wr_dummy(16*i+15 downto 16*i),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy(16*i+15 downto 16*i), rd_data(16*i+15 downto 16*i));
end generate RAM8;
RAM8A: if (data_bits mod 16) /= 0 generate
begin
CLEAR8: for i in last_in'high downto (data_bits mod 16) generate
begin
last_in(i) <= '0';
end generate CLEAR8;
last_in((data_bits mod 16)-1 downto 0) <= wr_data(data_bits-1 downto data_bits-(data_bits mod 16));
rd_data(data_bits-1 downto data_bits-(data_bits mod 16)) <= last_out((data_bits mod 16)-1 downto 0);
RAMX16A: component RAMB4_S16_S16 port map
(wr_en , always_one, reset, wr_clk, wr_addr, last_in(15 downto 0), wr_dummy2(15 downto 0),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy2(15 downto 0), last_out(15 downto 0));
end generate RAM8A;
end generate ADDR8;
--------------------------------------------
-- Use 512x8 RAM's
--------------------------------------------
ADDR9: if addr_bits=9 generate
begin
RAM9: for i in 0 to (data_bits/8)-1 generate
begin
RAMX8: component RAMB4_S8_S8 port map
(wr_en , always_one, reset, wr_clk, wr_addr, wr_data(8*i+7 downto 8*i), wr_dummy(8*i+7 downto 8*i),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy(8*i+7 downto 8*i), rd_data(8*i+7 downto 8*i));
end generate RAM9;
RAM9A: if (data_bits mod 8) /= 0 generate
begin
CLEAR9: for i in last_in'high downto (data_bits mod 8) generate
begin
last_in(i) <= '0';
end generate CLEAR9;
last_in((data_bits mod 8)-1 downto 0) <= wr_data(data_bits-1 downto data_bits-(data_bits mod 8));
rd_data(data_bits-1 downto data_bits-(data_bits mod 8)) <= last_out((data_bits mod 8)-1 downto 0);
RAMX8A: component RAMB4_S8_S8 port map
(wr_en , always_one, reset, wr_clk, wr_addr, last_in(7 downto 0), wr_dummy2(7 downto 0),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy2(7 downto 0), last_out(7 downto 0));
end generate RAM9A;
end generate ADDR9;
--------------------------------------------
-- Use 1k x 4 RAM's
--------------------------------------------
ADDR10: if addr_bits=10 generate
begin
RAM10: for i in 0 to (data_bits/4)-1 generate
begin
RAMX4: component RAMB4_S4_S4 port map
(wr_en , always_one, reset, wr_clk, wr_addr, wr_data(4*i+3 downto 4*i), wr_dummy(4*i+3 downto 4*i),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy(4*i+3 downto 4*i), rd_data(4*i+3 downto 4*i));
end generate RAM10;
RAM10A: if (data_bits mod 4) /= 0 generate
begin
CLEAR10: for i in last_in'high downto (data_bits mod 4) generate
begin
last_in(i) <= '0';
end generate CLEAR10;
last_in((data_bits mod 4)-1 downto 0) <= wr_data(data_bits-1 downto data_bits-(data_bits mod 4));
rd_data(data_bits-1 downto data_bits-(data_bits mod 4)) <= last_out((data_bits mod 4)-1 downto 0);
RAMX4A: component RAMB4_S4_S4 port map
(wr_en , always_one, reset, wr_clk, wr_addr, last_in(3 downto 0), wr_dummy2(3 downto 0),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy2(3 downto 0), last_out(3 downto 0));
end generate RAM10A;
end generate ADDR10;
--------------------------------------------
-- Use 2k x 2 RAM's
--------------------------------------------
ADDR11: if addr_bits=11 generate
begin
RAM11: for i in 0 to (data_bits/2)-1 generate
begin
RAMX2: component RAMB4_S2_S2 port map
(wr_en , always_one, reset, wr_clk, wr_addr, wr_data(2*i+1 downto 2*i), wr_dummy(2*i+1 downto 2*i),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy(2*i+1 downto 2*i), rd_data(2*i+1 downto 2*i));
end generate RAM11;
RAM11A: if (data_bits mod 2) /= 0 generate
begin
CLEAR11: for i in last_in'high downto (data_bits mod 2) generate
begin
last_in(i) <= '0';
end generate CLEAR11;
last_in(0) <= wr_data((data_bits mod 2)-1);
rd_data(data_bits-1) <= last_out((data_bits mod 2)-1);
RAMX2A: component RAMB4_S2_S2 port map
(wr_en , always_one, reset, wr_clk, wr_addr, last_in(1 downto 0), wr_dummy2(1 downto 0),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy2(1 downto 0), last_out(1 downto 0));
end generate RAM11A;
end generate ADDR11;
--------------------------------------------
-- Use 4x k 1 RAM's
--------------------------------------------
ADDR12: if addr_bits=12 generate
begin
RAM12: for i in 0 to data_bits-1 generate
begin
RAMX1: component RAMB4_S1_S1 port map
(wr_en , always_one, reset, wr_clk, wr_addr, wr_data(i), wr_dummy(i),
always_zero, always_one, reset, rd_clk, rd_addr, rd_dummy(i), rd_data(i));
end generate RAM12;
end generate ADDR12;
--------------------------------------------
-- Requires larger than a 4K x N RAM, use a 2-D array of 4Kx1's
--------------------------------------------
ADDRMAX: if addr_bits>12 generate
signal wr_en_col :std_logic_vector ((2**(addr_bits-12))-1 downto 0);
begin
RAMMAX: for i in 0 to data_bits-1 generate
begin
RAMXMAXA: component ram_x1_dp_block generic map
(addr_bits)
port map
(reset, wr_clk, wr_en, wr_addr, wr_data(i),
rd_clk, rd_addr, rd_data(i));
end generate RAMMAX;
end generate ADDRMAX;
end arch_ram_dp_block;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;
entity ram_dp is
generic (addr_bits :integer;
data_bits :integer;
register_out_flag :integer := 0;
block_type :integer := 0);
port (reset :in std_logic;
wr_clk :in std_logic;
wr_en :in std_logic;
wr_addr :in std_logic_vector (addr_bits-1 downto 0);
wr_data :in std_logic_vector (data_bits-1 downto 0);
rd_clk :in std_logic;
rd_addr :in std_logic_vector (addr_bits-1 downto 0);
rd_data :out std_logic_vector (data_bits-1 downto 0)
);
end ram_dp;
architecture arch_ram_dp of ram_dp is
begin
RAM_LUT: if (((2**addr_bits)*data_bits)<1024 and block_type=0)
or block_type=1
or register_out_flag=0 generate
begin
RAM_LUT0: component ram_dp_lut
generic map (addr_bits, data_bits, register_out_flag, block_type)
port map (reset, wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_addr, rd_data);
end generate RAM_LUT;
RAM_BLOCK: if (((2**addr_bits)*data_bits)>=1024 and block_type=0 and register_out_flag=1)
or (block_type=2 and register_out_flag=1) generate
begin
RAM_BLOCK0: component ram_dp_block
generic map (addr_bits, data_bits, register_out_flag, block_type)
port map (reset, wr_clk, wr_en, wr_addr, wr_data, rd_clk, rd_addr, rd_data);
end generate RAM_BLOCK;
end arch_ram_dp;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
----------------------------------------------------------------------------
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