ramlib_xil.vhd

8位RISC CPU的VERILOG编程 SOURCECODE

----------------------------------------------------------------------------
----------------------------------------------------------------------------
--  The Free IP Project
--  VHDL Free-RAM Core
--  (c) 1999, The Free IP Project and David Kessner
--
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for additional information.
--      http://www.free-ip.com
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


package ram_lib is
  component ram_dp
    generic (addr_bits		:integer;
             data_bits		:integer;
             register_out_flag	:integer := 0;
             block_type		:integer := 0);
    port (reset		:in  std_logic;
          wr_clk	:in  std_logic;
    	  wr_en	    	:in  std_logic;
          wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          wr_data	:in  std_logic_vector(data_bits-1 downto 0);
	  rd_clk	:in  std_logic;
          rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          rd_data	:out std_logic_vector(data_bits-1 downto 0)
         );
  end component;

  component ram_dp_lut
    generic (addr_bits		:integer;
             data_bits		:integer;
             register_out_flag	:integer := 0;
             block_type		:integer := 0);
    port (reset		:in  std_logic;
          wr_clk	:in  std_logic;
    	  wr_en	    	:in  std_logic;
          wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          wr_data	:in  std_logic_vector(data_bits-1 downto 0);
	  rd_clk	:in  std_logic;
          rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          rd_data	:out std_logic_vector(data_bits-1 downto 0)
         );
  end component;

  component ram_x1_dp_lut
    generic (addr_bits	:integer);
    port (clk		:in  std_logic;
    	  port1_wr	:in  std_logic;
          port1_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          port1_din	:in  std_logic;
          port1_dout	:out std_logic;
          port2_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          port2_dout	:out std_logic
         );
  end component;

  component ram_x1_dp_block
    generic (addr_bits	:integer);
    port (reset		:in  std_logic;
	  wr_clk	:in  std_logic;
	  wr_en		:in  std_logic;
	  wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
	  wr_data	:in  std_logic;
	  rd_clk	:in  std_logic;
	  rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
	  rd_data	:out std_logic
         );
  end component;

  component ram_dp_block
    generic (addr_bits		:integer;
             data_bits		:integer;
             register_out_flag	:integer := 0;
             block_type		:integer := 0);
    port (reset		:in  std_logic;
          wr_clk	:in  std_logic;
    	  wr_en	    	:in  std_logic;
          wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          wr_data	:in  std_logic_vector(data_bits-1 downto 0);
	  rd_clk	:in  std_logic;
          rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          rd_data	:out std_logic_vector(data_bits-1 downto 0)
         );
  end component;



  function slv_to_integer(x : std_logic_vector)
       return integer;
  function integer_to_slv(n, bits : integer)
      return std_logic_vector;  
end ram_lib;


----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

package body ram_lib is
  function slv_to_integer(x : std_logic_vector)
       return integer is
    variable n	:integer range 0 to (2**30 - 1);
  begin
    n := 0;
    for i in x'range loop
      n := n * 2;
      case x(i) is
        when '1' | 'H' => n := n + 1;
        when '0' | 'L' => null;
        when others =>	  null;
      end case;
    end loop;

    return n;
  end slv_to_integer;

  function integer_to_slv(n, bits : integer)
      return std_logic_vector is
    variable x		:std_logic_vector(bits-1 downto 0);
    variable tempn	:integer;
  begin
    x := (others => '0');
    tempn := n;
    for i in x'reverse_range loop
      if (tempn mod 2) = 1 then
        x(i) := '1';
      end if;
      tempn := tempn / 2;
    end loop;

    return x;
  end integer_to_slv;
end ram_lib;


----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_x1_dp_lut is
    generic (addr_bits	:integer);
    port (clk		:in std_logic;
    	  port1_wr	:in std_logic;
          port1_addr	:in std_logic_vector (addr_bits-1 downto 0);
          port1_din	:in std_logic;
          port1_dout	:out std_logic;
          port2_addr	:in std_logic_vector (addr_bits-1 downto 0);
          port2_dout	:out std_logic
         );
end ram_x1_dp_lut;


architecture arch_ram_x1_dp_lut of ram_x1_dp_lut is
  component RAM16X1D
      port (D, WE, WCLK, A3, A2, A1, A0,
            DPRA3, DPRA2, DPRA1, DPRA0: in std_logic;
            SPO,DPO: out std_logic);
  end component;

  signal d_port1_dout :std_logic_vector ((2**(addr_bits-4))-1 downto 0);
  signal d_port2_dout :std_logic_vector ((2**(addr_bits-4))-1 downto 0);
  signal write_enable :std_logic_vector ((2**(addr_bits-4))-1 downto 0);

begin
  ------------------------------------
  -- Array of RAM Blocks
  RAMX1_DP: for i in (2**(addr_bits-4))-1 downto 0 generate
  begin
    RAM_LUT: component RAM16X1D port map
            (D=>port1_din,
             WE=>write_enable(i),
             WCLK=>clk,
             A3=>port1_addr(3),
             A2=>port1_addr(2),
             A1=>port1_addr(1),
             A0=>port1_addr(0),
             DPRA3=>port2_addr(3),
             DPRA2=>port2_addr(2),
             DPRA1=>port2_addr(1),
             DPRA0=>port2_addr(0),
             SPO=>d_port1_dout(i),
             DPO=>d_port2_dout(i));
  end generate RAMX1_DP;


  ------------------------------------
  -- Generate the write enables
  WE_GEN_SMALL: if addr_bits<=4 generate
  begin
    write_enable(0) <= port1_wr;
  end generate WE_GEN_SMALL;
  
  WE_GEN_LARGE: if addr_bits>4 generate
  begin
    WE_GEN:  for i in (2**(addr_bits-4))-1 downto 0 generate
    begin
      process (port1_wr, port1_addr)
      begin
        if integer_to_slv(i, addr_bits-4) = port1_addr(addr_bits-1 downto 4) and port1_wr='1' then
          write_enable(i) <= '1';
        else
          write_enable(i) <= '0';
        end if;
      end process;
    end generate WE_GEN;
  end generate WE_GEN_LARGE;


  ------------------------------------
  -- Mux the data outputs
  MUX_SMALL: if addr_bits<=4 generate
  begin
    port1_dout <= d_port1_dout(0);
    port2_dout <= d_port2_dout(0);
  end generate MUX_SMALL;

  MUX_LARGE: if addr_bits>4 generate
  begin
    port1_dout <= d_port1_dout(slv_to_integer(port1_addr(addr_bits-1 downto 4)));
    port2_dout <= d_port2_dout(slv_to_integer(port2_addr(addr_bits-1 downto 4)));
  end generate MUX_LARGE;

end arch_ram_x1_dp_lut;


----------------------------------------------------------------------------
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_dp_lut is
    generic (addr_bits		:integer;
             data_bits		:integer;
             register_out_flag	:integer := 0;
             block_type		:integer := 0);
    port (reset		:in  std_logic;
          wr_clk	:in  std_logic;
    	  wr_en	    	:in  std_logic;
          wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          wr_data	:in  std_logic_vector (data_bits-1 downto 0);
	  rd_clk	:in  std_logic;
          rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
          rd_data	:out std_logic_vector (data_bits-1 downto 0)
         ); 
end ram_dp_lut;


architecture arch_ram_dp_lut of ram_dp_lut is
  signal rd_data_int	:std_logic_vector (data_bits-1 downto 0);
  
  signal wr_dout	:std_logic_vector (data_bits-1 downto 0);
begin
  RAM_DP:  for i in data_bits-1 downto 0 generate
  begin
    RAMX1: component ram_x1_dp_lut
      generic map (addr_bits)
      port map (wr_clk, wr_en, wr_addr, wr_data(i), wr_dout(i),
                rd_addr, rd_data_int(i));
  end generate RAM_DP;

  RAM_BUF:  if register_out_flag=0 generate
  begin
    rd_data <= rd_data_int;
  end generate RAM_BUF;

  RAM_REG:  if register_out_flag/=0 generate
  begin
    process (reset, rd_clk)
    begin
      if reset='1' then
        rd_data <= (others=>'0');
      elsif rd_clk'event and rd_clk='1' then
        rd_data <= rd_data_int;
      end if;
    end process;
  end generate RAM_REG; 
end arch_ram_dp_lut;


----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Note:  This entity only works for addr_bits>12
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.ram_lib.all;

entity ram_x1_dp_block is
    generic (addr_bits	:integer);
    port (reset		:in  std_logic;
	  wr_clk	:in  std_logic;
	  wr_en		:in  std_logic;
	  wr_addr	:in  std_logic_vector (addr_bits-1 downto 0);
	  wr_data	:in  std_logic;
	  rd_clk	:in  std_logic;
	  rd_addr	:in  std_logic_vector (addr_bits-1 downto 0);
	  rd_data	:out std_logic
         );
end ram_x1_dp_block;


architecture arch_ram_x1_dp_block of ram_x1_dp_block is
  component RAMB4_S1_S1
    port (WEA, ENA, RSTA, CLKA	:in  std_logic;
          ADDRA			:in  std_logic_vector (11 downto 0);
          DIA			:in  std_logic;
          DOA			:out std_logic;
          WEB, ENB, RSTB, CLKB	:in  std_logic;
          ADDRB			:in  std_logic_vector (11 downto 0);
          DIB			:in  std_logic;
          DOB			:out std_logic
          );
  end component;

  signal d_port1_dout :std_logic_vector ((2**(addr_bits-12))-1 downto 0);
  signal d_port2_dout :std_logic_vector ((2**(addr_bits-12))-1 downto 0);
  signal write_enable :std_logic_vector ((2**(addr_bits-12))-1 downto 0);

  signal rd_addr_reg  :std_logic_vector (addr_bits-12-1 downto 0);
  
  signal always_one	:std_logic;
  signal always_zero	:std_logic;

begin
  always_one <= '1';
  always_zero <= '0';
  
  ------------------------------------
  -- Array of RAM Blocks
  RAMX1_DP: for i in (2**(addr_bits-12))-1 downto 0 generate
  begin
    RAMX1:  component RAMB4_S1_S1 port map
          (write_enable(i), always_one, reset, wr_clk, wr_addr(11 downto 0), wr_data,     d_port1_dout(i),
          always_zero,      always_one, reset, rd_clk, rd_addr(11 downto 0), always_zero, d_port2_dout(i));
  end generate RAMX1_DP;