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<h1 align="left"><!--mstheme--><font color="#660033"><a name="Table Of Contents">Table Of Contents</a><!--mstheme--></font></h1>
<ol>
<li><span style="font-size:10.0pt"><a href="#Introduction">Introduction</a></span></li>
<li><span style="font-size:10.0pt"><a href="#QuickStart">Quick Start</a></span></li>
<li><span style="font-size:10.0pt"><a href="#SystemArchitecture">System Architecture</a></span></li>
<li><span style="font-size:10.0pt"><a href="#Compatibility">Compatibility with Microchip 16C57 Devices</a></span></li>
<li><span style="font-size:10.0pt"><a href="#ModuleHierarchy">Module Hierarchy</a></span></li>
<li><span style="font-size:10.0pt"><a href="#Synthesis">Synthesis</a></span></li>
<li><span style="font-size:10.0pt"><a href="#CPUModule">CPU Module</a></span></li>
<li><span style="font-size:10.0pt"><a href="#MemoryInterfaces">Memory Interfaces</a></span></li>
<li><span style="font-size:10.0pt"><a href="#ALU">ALU</a></span></li>
<li><span style="font-size:10.0pt"><a href="#InstructionDecoder">Instruction Decoder</a></span></li>
<li><span style="font-size:10.0pt"><a href="#RegisterFile">Register File</a></span></li>
<li><span style="font-size:10.0pt"><a href="#FirmwareDevelopment">Firmware Development</a></span></li>
<li><span style="font-size:10.0pt"><a href="#Expansion">Expansion</a></span></li>
<li><span style="font-size:10.0pt"><a href="#TestPrograms">Test Programs</a></span></li>
<li><span style="font-size:10.0pt"><a href="#Bugs">Bugs</a></span></li>
</ol>
<h1><!--mstheme--><font color="#660033"><a name="Introduction"><span style="font-size:13.5pt;font-family:Arial">Introduction<o:p>
</o:p>
</span></a><!--mstheme--></font></h1>
<p><span style="font-size:10.0pt">The Free-RISC8 is a Verilog implementation of
a simple 8-bit processor. The RISC8 is binary code compatible with the Microchip
16C57 processor. Code may be developed and debugged using tools available from a
number of 3<sup>rd</sup> Party tool developers. Programs existing for the 16C57
may be ported to the RISC8 for use in an FPGA, etc.<o:p>
</o:p>
</span></p>
<p><span style="font-size:10.0pt">The design is synthesizable and has been used
by various people in the past within ASICs as well as FPGAs. The package
consists of the following Verilog and C files:<o:p>
</o:p>
</span></p>
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<p align="center" style="text-align:center"><b><i><span style="font-size:10.0pt">File</span></i></b></p>
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<p align="center" style="text-align:center"><b><i><span style="font-size:10.0pt">Description</span></i></b></p>
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<p><span style="font-size:10.0pt">test.v</span></p>
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<p><span style="font-size:10.0pt">Top-level testbench, including the
behavioral Verilog program memory</span></p>
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<p><span style="font-size:10.0pt">cpu.v</span></p>
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<p><span style="font-size:10.0pt">Top-level synthesizable module.</span></p>
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<p><span style="font-size:10.0pt">idec.v</span></p>
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<p><span style="font-size:10.0pt">The Instruction Decoder. This module is
instanced underneath the cpu module.</span></p>
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<p><span style="font-size:10.0pt">alu.v</span></p>
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<p><span style="font-size:10.0pt">The ALU. This module is instanced
underneath the cpu module.</span></p>
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<p><span style="font-size:10.0pt">regs.v</span></p>
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<p><span style="font-size:10.0pt">The Register File. This module is
instanced underneath the cpu module.</span></p>
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<p><span style="font-size:10.0pt">exp.v</span></p>
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<p><span style="font-size:10.0pt">Optional Expansion Module. This is an
example module that shows how an expansion circuit is added onto the
design. The module supplied with this release implements a very simple DDS
(Direct Digital Synthesis) circuit that is used for the DDS demo.</span></p>
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<p><span style="font-size:10.0pt">dram.v</span></p>
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<p><span style="font-size:10.0pt">Memory model for Register File
慏抋ta memory (it抯 a Synchronous RAM)</span></p>
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<p><span style="font-size:10.0pt">pram.v</span></p>
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<p><span style="font-size:10.0pt">Memory model for Program Memory
慞抋ta memory (it抯 a Synchronous RAM)</span></p>
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<p><span style="font-size:10.0pt">hex2v.c,<br>
hex2v.exe</span></p>
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<p><span style="font-size:10.0pt">A C program that translates Intel HEX
format data into the Verilog $readmemh compatible .ROM file.</span></p>
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<td width="14%" valign="top" style="width:14.0%;padding:5.25pt 5.25pt 5.25pt 5.25pt"><!--mstheme--><font face="Book Antiqua, Times New Roman, Times">
<p><span style="font-size:10.0pt">basic.asm,<br>
basic.hex,<o:p><br>
basic.rom</span></p>
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<td width="86%" valign="top" style="width:86.0%;padding:5.25pt 5.25pt 5.25pt 5.25pt"><!--mstheme--><font face="Book Antiqua, Times New Roman, Times">
<p><span style="font-size:10.0pt">The "Basic Confidence" test
program which exercises all the instructions.</span></p>
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<p><span style="font-size:10.0pt">dds.asm,<o:p><br>
dds.hex,<o:p><br>
dds.rom</span></p>
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<p><span style="font-size:10.0pt">A demo that uses the DDS circuit. The
demo outputs an FSK "burst".</span></p>
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<p><span style="font-size:10.0pt">runit</span></p>
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<p><span style="font-size:10.0pt">A script containing the Verilog command
line required.</span></p>
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</tr>
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<p><span style="font-size:10.0pt"> <o:p>
</o:p>
</span></p>
<h1><!--mstheme--><font color="#660033"><a name="QuickStart"><span style="font-size:13.5pt;font-family:Arial">Quick Start<o:p>
</o:p>
</span></a><!--mstheme--></font></h1>
<p><span style="font-size:10.0pt">Extract all the files from the supplied ZIP
into a new directory. Once all the files have been extracted from the archive,
invoke your Verilog simulator specifying all the Verilog files (the 憆unit⌨️ 快捷键说明
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