test.v

8位RISC CPU的VERILOG编程 SOURCECODE

/* ***********************************************************************
  The Free IP Project
  Free-RISC8 -- Verilog 8-bit Microcontroller
  (c) 1999, The Free IP Project and Thomas Coonan


  FREE IP GENERAL PUBLIC LICENSE
  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION

  1.  You may copy and distribute verbatim copies of this core, as long
      as this file, and the other associated files, remain intact and
      unmodified.  Modifications are outlined below.  
  2.  You may use this core in any way, be it academic, commercial, or
      military.  Modified or not.  
  3.  Distribution of this core must be free of charge.  Charging is
      allowed only for value added services.  Value added services
      would include copying fees, modifications, customizations, and
      inclusion in other products.
  4.  If a modified source code is distributed, the original unmodified
      source code must also be included (or a link to the Free IP web
      site).  In the modified source code there must be clear
      identification of the modified version.
  5.  Visit the Free IP web site for additional information.
      http://www.free-ip.com

*********************************************************************** */

`timescale 1ns / 10ps

module test;

// For 50Mhz, period is 20ns, so set CLKHI to 10 and CLKLO to 10
parameter CLKHI = 10;
parameter CLKLO = 10;

// Define some codes for each instruction opcode.  These have nothing to do
// with the actual encoding of the instructions.  This is for display purposes.
//
parameter NOP	= 1;
parameter MOVWF	= 2;
parameter CLRW	= 3;
parameter CLRF	= 4;
parameter SUBWF	= 5;
parameter DECF	= 6;
parameter IORWF	= 7;
parameter ANDWF	= 8;
parameter XORWF	= 9;
parameter ADDWF	= 10;
parameter MOVF	= 11;
parameter COMF	= 12;
parameter INCF	= 13;
parameter DECFSZ = 14;
parameter RRF	= 15;
parameter RLF	= 16;
parameter SWAPF	= 17;
parameter INCFSZ = 18;
parameter BCF	= 19;
parameter BSF	= 20;
parameter BTFSC	= 21;
parameter BTFSS	= 22;
parameter OPTION = 23;
parameter SLEEP	= 24;
parameter CLRWDT = 25;
parameter TRIS	= 26;
parameter RETLW	= 27;
parameter CALL	= 28;
parameter GOTO	= 29;
parameter MOVLW	= 30;
parameter IORLW	= 31;
parameter ANDLW	= 32;
parameter XORLW	= 33;

// *** Basic Interface to the PICCPU
reg		clk;
reg		reset;

// Declare I/O Port connections
reg  [7:0]	porta; // INPUT
wire [7:0]	portb; // OUTPUT
wire [7:0]	portc; // OUTPUT

// Declare ROM and rom signals
wire [10:0]	pramaddr;
wire [11:0]	pramdata;

// *** Expansion Interface
wire [7:0]	expdin;
wire [7:0]	expdout;
wire [6:0]	expaddr;
wire		expread;
wire		expwrite;

// Debug output ports on the core.  These are just internal signals brought out so
// they can be observed.
//
wire [7:0]	debugw;
wire [10:0]	debugpc;
wire [11:0]	debuginst;
wire [7:0]	debugstatus;
 
// Instantiate one CPU to be tested.
cpu cpu (
   .clk		(clk),
   .reset	(reset),
   .paddr	(pramaddr),
   .pdata	(pramdata),
   .portain	(porta),
   .portbout	(portb),
   .portcout	(portc),
   .expdin	(expdin),
   .expdout	(expdout),
   .expaddr	(expaddr),
   .expread	(expread),
   .expwrite	(expwrite),
   .debugw	(debugw),
   .debugpc	(debugpc),
   .debuginst	(debuginst),
   .debugstatus	(debugstatus)
);

// Instantiate the Program RAM.
pram pram (
   .clk		(clk),
   .address	(pramaddr),
   .we		(1'b0),			// This testbench doesn't allow writing to PRAM
   .din		(12'b000000000000),	// This testbench doesn't allow writing to PRAM
   .dout	(pramdata)
);

// Output of the DDS in the Expansion module (see section on the DDS Demo in docs).
wire [7:0] dds_out;

// Instantiate one PICEXP (Expansion) module.  This one is a DDS circuit.
exp exp(
   .clk		(clk),
   .reset	(reset),
   .expdin	(expdin),
   .expdout	(expdout),
   .expaddr	(expaddr),
   .expread	(expread),
   .expwrite	(expwrite),
   .dds_out	(dds_out)
);

// This is the only initial block in the test module and this is where
// you select what test you want to do.
//
initial begin
   $display ("Free-RISC8.  Version 1.0");
   
   // Just uncomment out the test you want to run!
   
   // ** This is our top-level "Basic Confidence" test.
   basic;
   
   // ** This is the DDS example.  Make sure the DDS circuit is in the Verilog command line.
   //dds_test;
end

// Event should be emitted by any task to kill simulation.  Tasks should
// use this to close files, etc.
//
event ENDSIM;

// Capture some data
task capture_data;
   begin
      $dumpfile ("risc8.vcd");
      $dumpvars (0, test);
      @(ENDSIM);
      $dumpflush;
   end
endtask

// Reset
task reset_pic;
   begin
      reset = 1;
      #200;
      reset = 0;
      $display ("End RESET.");
   end
endtask
  
// Drive the clock input
task drive_clock;
   begin
      clk  = 0;
      forever begin
         #(CLKLO) clk = 1;
         #(CLKHI) clk = 0;
      end
   end
endtask

// *************  BASIC CONFIDENCE Test Tasks **************
//
// BASIC CONFIDENCE Test.
//
// This task will fork off all the other necessary tasks to cause reset, drive the clock, etc. etc.
//
// 
task basic;
   
   integer  num_outputs;
   integer  num_matches;
   integer  num_mismatches;
   
   begin
      $display ("Free-RISC8 1.0.  This is the BASIC CONFIDENCE TEST.");
      #1;
   
      $display ("Loading program memory with %s", "basic.rom");
      $readmemh ("basic.rom", pram.mem);

      fork
         // Capture data
         capture_data;
         
         // Run the clock
         drive_clock;
         
         // Do a reset
         reset_pic;
         
         // Monitor the number of cycles and set an absolute maximum number of cycles.
         monitor_cycles (5000);
         
         // More specific monitors
         //monitor_inst;
         monitor_portb;
         monitor_portc;
         
         // Drive PORTA with a toggling pattern.  This is for one of the subtests.
         //
         basic_drive_porta;
         
         // Monitor the counting pattern on PORTB.  This is our self-checking scheme for the test.
         // 
         begin
            // 
            num_outputs = 9;  // Expect exactly 7 changes on the PORTB (0..6).
            
            // Call the following task which will watch PORTB for the patterns.
            //
            basic_monitor_output_signature (num_outputs, num_matches, num_mismatches);
            
            // See how we did!
            repeat (2) @(posedge clk);
            $display ("Done monitoring for output signature.  %0d Matches, %0d Mismatches.", num_matches, num_mismatches);
            if (num_matches == num_outputs && num_mismatches == 0) begin
               $display ("SUCCESS.");
            end
            else begin
               $display ("Test FAILED!!");
            end
            
            // We are done.  Throw the ENDSIM event.
            ->ENDSIM;
            #0;
            $finish;
         end
         
         // Catch end of simulation event due to max number of cycles or pattern from PIC code.
         begin
            @(ENDSIM);  // Catch the event.
            
            // Got it!
            $display ("End of simulation signalled.  Killing simulation in a moment.");
            #0; // Let anything else see this event...
            $finish;
         end
      join
   end
endtask

// Monitor PORTB for an incrementing pattern.  This is how we are doing our self-checking.
// A good run will count from ZERO up to some number.
//
task basic_monitor_output_signature;
   input   num_outputs;
   output  num_matches;
   output  num_mismatches;
   
   integer  num_outputs;
   integer  num_matches;
   integer  num_mismatches;
   
   integer      i;
   reg [7:0]    expected_output;
   begin
      num_matches    = 0;
      num_mismatches = 0;
      
      expected_output = 8'h00;
      
      i = 0;
      while (i < num_outputs) begin
         // Wait for any change on output port B.
         @(portb);
         #1;  // Wait for a moment for any wiggling on different 
              // bits to seetle out, just in case there's any gate-level going on..
         if (portb == expected_output) begin
            $display ("MONITOR_OUTPUT_SIGNATURE: Expected output observed on PORTB: %h", portb);
            num_matches = num_matches + 1;
         end
         else begin
            $display ("MONITOR_OUTPUT_SIGNATURE: Unexpected output on PORTB: %h", portb);
            num_mismatches = num_mismatches + 1;
         end
            
         expected_output = expected_output + 1;
         i = i + 1;
      end
   end
endtask

task basic_drive_porta;
   begin
      forever begin
         porta = 8'h55;
         repeat (32) @(posedge clk);
         porta = 8'hAA;
         repeat (32) @(posedge clk);
      end
   end
endtask

// *************  DDS Demo Test Tasks **************
//
// DDS Test.
//
// This task will fork off all the other necessary tasks to cause reset, drive the clock, etc. etc.
//
// In a waveform viewer, check out PORTC[1:0] and also check out the 'dds_out' output.
// You should see a modulated sine wave (e.g. FSK).