readme.txt

8位RISC CPU的VERILOG编程 SOURCECODE

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--  The Free IP Project
--  VHDL Free-RISC8 Core
--  (c) 1999-2000, The Free IP Project
--
--
--  FREE IP GENERAL PUBLIC LICENSE
--  TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION
--
--  1.  You may copy and distribute verbatim copies of this core, as long
--      as this file, and the other associated files, remain intact and
--      unmodified.  Modifications are outlined below.  
--  2.  You may use this core in any way, be it academic, commercial, or
--      military.  Modified or not.  
--  3.  Distribution of this core must be free of charge.  Charging is
--      allowed only for value added services.  Value added services
--      would include copying fees, modifications, customizations, and
--      inclusion in other products.
--  4.  If a modified source code is distributed, the original unmodified
--      source code must also be included (or a link to the Free IP web
--      site).  In the modified source code there must be clear
--      identification of the modified version.
--  5.  Visit the Free IP web site for documentation and additional 
--      information.  http://www.free-ip.com
--
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This is version 1.1 (Feb 2000) of the Free-RISC8 core


HTML documentation can be found in the www/ directory.
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