xsuartregs.h

usb 检验程序

/******************************************************************************
**
**  COPYRIGHT (C) 2000 Intel Corporation
**
**	FILENAME			:	XsUartRegs.h
**  Reference FILENAME	:   xsuart.h
**
**  PURPOSE:		This file containes the UART's register definitions		       
**
**  LAST MODIFIED: 12/20/2000
******************************************************************************/

#ifndef __XSUART_REGS_H
#define __XSUART_REGS_H

/*
************************************************************************************
*                             Register Physical Addresses 
************************************************************************************
*/
#define RBR_IDX	0	
#define THR_IDX	0	
#define IER_IDX	1	
#define IIR_IDX	2	
#define FCR_IDX	2	
#define LCR_IDX	3	
#define MCR_IDX	4	
#define LSR_IDX	5	
#define MSR_IDX	6	
#define SPR_IDX	7	
#define ISR_IDX	8	
#define DLL_IDX	0	
#define DLH_IDX	1	

#define FFUARTREG_PHY_BASE_ADDR	(0x40100000)	// FFUART Base Register Location
#define FFUART_FFRBR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x0)
#define FFUART_FFTHR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x0)
#define FFUART_FFIER_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x4)
#define FFUART_FFIIR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x8)
#define FFUART_FFFCR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x8)
#define FFUART_FFLCR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0xC)
#define FFUART_FFMCR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x10)
#define FFUART_FFLSR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x14)
#define FFUART_FFMSR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x18)
#define FFUART_FFSPR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x1C)
#define FFUART_FFISR_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x20)
#define FFUART_FFDLL_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x0)
#define FFUART_FFDLH_ADDR	(FFUARTREG_PHY_BASE_ADDR+0x4)
#define FFUART_FFRBR	*(volatile unsigned int *)FFUART_FFRBR_ADDR
#define FFUART_FFTHR	*(volatile unsigned int *)FFUART_FFTHR_ADDR
#define FFUART_FFIER	*(volatile unsigned int *)FFUART_FFIER_ADDR
#define FFUART_FFIIR	*(volatile unsigned int *)FFUART_FFIIR_ADDR
#define FFUART_FFFCR	*(volatile unsigned int *)FFUART_FFFCR_ADDR
#define FFUART_FFLCR	*(volatile unsigned int *)FFUART_FFLCR_ADDR
#define FFUART_FFMCR	*(volatile unsigned int *)FFUART_FFMCR_ADDR
#define FFUART_FFLSR	*(volatile unsigned int *)FFUART_FFLSR_ADDR
#define FFUART_FFMSR	*(volatile unsigned int *)FFUART_FFMSR_ADDR
#define FFUART_FFSPR	*(volatile unsigned int *)FFUART_FFSPR_ADDR
#define FFUART_FFISR	*(volatile unsigned int *)FFUART_FFISR_ADDR
#define FFUART_FFDLL	*(volatile unsigned int *)FFUART_FFDLL_ADDR
#define FFUART_FFDLH	*(volatile unsigned int *)FFUART_FFDLH_ADDR

#define BTUARTREG_PHY_BASE_ADDR	(0x40200000)	// BTUART Base Register Location
#define BTUART_BTRBR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x0)
#define BTUART_BTTHR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x0)
#define BTUART_BTIER_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x4)
#define BTUART_BTIIR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x8)
#define BTUART_BTFCR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x8)
#define BTUART_BTLCR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0xC)
#define BTUART_BTMCR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x10)
#define BTUART_BTLSR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x14)
#define BTUART_BTMSR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x18)
#define BTUART_BTSPR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x1C)
#define BTUART_BTISR_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x20)
#define BTUART_BTDLL_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x0)
#define BTUART_BTDLH_ADDR	(BTUARTREG_PHY_BASE_ADDR+0x4)
#define BTUART_BTRBR	*(volatile unsigned int *)BTUART_BTRBR_ADDR
#define BTUART_BTTHR	*(volatile unsigned int *)BTUART_BTTHR_ADDR
#define BTUART_BTIER	*(volatile unsigned int *)BTUART_BTIER_ADDR
#define BTUART_BTIIR	*(volatile unsigned int *)BTUART_BTIIR_ADDR
#define BTUART_BTFCR	*(volatile unsigned int *)BTUART_BTFCR_ADDR
#define BTUART_BTLCR	*(volatile unsigned int *)BTUART_BTLCR_ADDR
#define BTUART_BTMCR	*(volatile unsigned int *)BTUART_BTMCR_ADDR
#define BTUART_BTLSR	*(volatile unsigned int *)BTUART_BTLSR_ADDR
#define BTUART_BTMSR	*(volatile unsigned int *)BTUART_BTMSR_ADDR
#define BTUART_BTSPR	*(volatile unsigned int *)BTUART_BTSPR_ADDR
#define BTUART_BTISR	*(volatile unsigned int *)BTUART_BTISR_ADDR
#define BTUART_BTDLL	*(volatile unsigned int *)BTUART_BTDLL_ADDR
#define BTUART_BTDLH	*(volatile unsigned int *)BTUART_BTDLH_ADDR

#define STUARTREG_PHY_BASE_ADDR	(0x40700000)	// STUART Base Register Location
#define STUART_STRBR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x0)
#define STUART_STTHR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x0)
#define STUART_STIER_ADDR	(STUARTREG_PHY_BASE_ADDR+0x4)
#define STUART_STIIR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x8)
#define STUART_STFCR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x8)
#define STUART_STLCR_ADDR	(STUARTREG_PHY_BASE_ADDR+0xC)
#define STUART_STMCR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x10)
#define STUART_STLSR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x14)
#define STUART_STMSR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x18)
#define STUART_STSPR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x1C)
#define STUART_STISR_ADDR	(STUARTREG_PHY_BASE_ADDR+0x20)
#define STUART_STDLL_ADDR	(STUARTREG_PHY_BASE_ADDR+0x0)
#define STUART_STDLH_ADDR	(STUARTREG_PHY_BASE_ADDR+0x4)
#define STUART_STRBR	*(volatile unsigned int *)STUART_STRBR_ADDR
#define STUART_STTHR	*(volatile unsigned int *)STUART_STTHR_ADDR
#define STUART_STIER	*(volatile unsigned int *)STUART_STIER_ADDR
#define STUART_STIIR	*(volatile unsigned int *)STUART_STIIR_ADDR
#define STUART_STFCR	*(volatile unsigned int *)STUART_STFCR_ADDR
#define STUART_STLCR	*(volatile unsigned int *)STUART_STLCR_ADDR
#define STUART_STMCR	*(volatile unsigned int *)STUART_STMCR_ADDR
#define STUART_STLSR	*(volatile unsigned int *)STUART_STLSR_ADDR
#define STUART_STMSR	*(volatile unsigned int *)STUART_STMSR_ADDR
#define STUART_STSPR	*(volatile unsigned int *)STUART_STSPR_ADDR
#define STUART_STISR	*(volatile unsigned int *)STUART_STISR_ADDR
#define STUART_STDLL	*(volatile unsigned int *)STUART_STDLL_ADDR
#define STUART_STDLH	*(volatile unsigned int *)STUART_STDLH_ADDR
/*
************************************************************************************
*                             Bits and Length Definitions 
************************************************************************************
*/
// Bits Definitions for IER Reg.
// Note: 
//      - XX_OFS means the bit offset 
//	    - XX_SZ means the field length


#define	IER_RAVIE_OFS	(0)
#define	IER_TIE_OFS		(1)
#define	IER_RLSE_OFS	(2)
#define	IER_MIE_OFS		(3)
#define	IER_RTOIE_OFS	(4)
#define	IER_NRZE_OFS	(5)
#define	IER_UUE_OFS		(6)
#define	IER_DMAE_OFS	(7)

// Bits Definitions for Interrupt Identification Reg. (IIR)
// Note: IIR (read only) is located at the same address as the FCR (write only)

#define IIR_IP_OFS  		(0)
#define IIR_IID_OFS     	(1)
#define IIR_IID_SZ	     	(2)
#define IIR_TOD_OFS			(3)
#define IIR_IID3_OFS     	(IIR_TOD_OFS)
#define IIR_FIFOES_OFS		(6)
#define IIR_FIFOES_SZ		(2)

  
// Bits Definitions for FIFO Control Register

#define FCR_TRFIFOE_OFS		(0)
#define FCR_RESETRF_OFS		(1)
#define FCR_RESETTF_OFS		(2)
#define FCR_ITL_OFS			(6)
#define FCR_ITL_SZ			(2)


// Bits Definitions for Line Control Reg. (LCR)

#define LCR_WLS_OFS			(0)
#define LCR_WLS_SZ			(2)
#define LCR_STB_OFS 		(2)
#define LCR_PEN_OFS 		(3)
#define LCR_EPS_OFS 		(4)
#define LCR_STKYP_OFS		(5)
#define LCR_SB_OFS  		(6)
#define LCR_DLAB_OFS 		(7)

// Bits Definitions for Line Status Reg. (LSR)

#define LSR_DR_OFS	 		(0)
#define LSR_OE_OFS	 		(1)
#define LSR_PE_OFS	 		(2)
#define LSR_FE_OFS	 		(3)
#define LSR_BI_OFS	 		(4)
#define LSR_TDRQ_OFS 		(5)
#define LSR_TEMT_OFS 		(6)
#define LSR_FIFOE_OFS	 	(7)

// Bits Definitions for Modem Control Reg.

#define MCR_DTR_OFS	 		(0)
#define MCR_RTS_OFS	 		(1)
#define MCR_OUT1_OFS 		(2)
#define MCR_OUT2_OFS 		(3)
#define MCR_LOOP_OFS 		(4)

// Bits Definitions for Modem Status Reg. (MSR) 
//		notes: some errors exist in MSR difine in xsuart.h

#define MSR_DCTS_OFS 		(0)
#define MSR_DDSR_OFS 		(1)
#define MSR_TERI_OFS	 	(2)
#define MSR_DDCD_OFS	 	(3)
#define MSR_CTS_OFS	 		(4)
#define MSR_DSR_OFS 		(5)
#define MSR_RI_OFS 			(6)
#define MSR_DCD_OFS	 		(7)

// Bits Definitions for Infrared Selection Reg. (ISR)

#define ISR_XMITIR_OFS 		(0)
#define ISR_RCVEIR_OFS 		(1)
#define ISR_XMODE_OFS 		(2)
#define ISR_TXPL_OFS 		(3)
#define ISR_RXPL_OFS 		(4)

/*
************************************************************************************
*                             CONSTANTS 
************************************************************************************
*/


/*
************************************************************************************
*                            DATA TYPES 
************************************************************************************
*/
#define DLL_FIELD UDATA
#define DLH_FIELD IER
// UART registers
// This type is used by FFUART, BTUART and STUART
typedef struct UartRegsS {
	unsigned int	UDATA;	// Receive Buffer Reg. (RBR), Transmit Holding Reg. (THR) and DLL
	//unsigned int	DLL;
	unsigned int	IER;	// Interrupt Enable Reg. (IER) and Baud Divisor Higher Byte Reg. (DLH)
	//unsigned int	DLH;
	unsigned int	FCR;	// Interrupt ID Reg. (read only) and FIFO Control Reg. (write only)
	unsigned int	LCR;	// Line Control Reg. 
	unsigned int	MCR;	// Modem Control Reg.
	unsigned int	LSR;	// Line Status Reg.
	unsigned int	MSR;	// Modem Status Reg.
	unsigned int	SPR;	// Scratch Pad Reg.
	unsigned int	ISR;	// Slow Infrared Select Reg.	
} UartRegsT;

// Masks for IER Reg.
// Note: 
//      - user needs to program the GPIO reg. before enabling the unit
//	    - NRZ is used in UART mode only, not for infrared mode
//		- user needs to make sure that DMA and TIE and RAVIE are not set to 1 at the same time	

#define	IER_RAVIE	(0x1 << 0)
#define	IER_TIE		(0x1 << 1)
#define	IER_RLSE	(0x1 << 2)
#define	IER_MIE		(0x1 << 3)
#define	IER_RTOIE	(0x1 << 4)
#define	IER_NRZE	(0x1 << 5)
#define	IER_UUE		(0x1 << 6)
#define	IER_DMAE	(0x1 << 7)

// Masks for Interrupt Identification Reg. (IIR)
// Note: IIR (read only) is located at the same address as the FCR (write only)

#define IIR_IP  		(0x1 << 0)
#define IIR_RLS     	(0x3 << 1)
#define IIR_RDA			(0x1 << 2)
#define IIR_TOD			(0x3 << 2)
#define IIR_TFIFO		(0x1 << 1)
#define IID_MODS		(0x0 << 3)
#define IID_FIFOES		(0x3 << 6)
  
// Masks for FIFO Control Register

#define FCR_TRFIFOD		(0x0 << 0)
#define FCR_TRFIFOE		(0x1 << 0)
#define FCR_RESETRF		(0x1 << 1)
#define FCR_RESETTF		(0x1 << 2)
#define FCR_ITL1		(0x0 << 7)
#define FCR_ITL8		(0x1 << 6)
#define FCR_ITL16		(0x1 << 7)
#define FCR_ITL32		(0x3 << 6)
#define FCR_ENABLED     (FCR_TRFIFOE | FCR_RESETRF | FCR_RESETTF)

// Masks for Line Control Reg. (LCR)

#define LCR_WLS5		(0x0 << 0)
#define LCR_WLS6		(0x1 << 0)
#define LCR_WLS7		(0x1 << 1)
#define LCR_WLS8		(0x3 << 0)
#define LCR_STB 		(0x1 << 2)
#define LCR_PEN 		(0x1 << 3)
#define LCR_EPSO 		(0x1 << 4)
#define LCR_EPSE 		(0x0 << 4)
#define LCR_STKYP		(0x1 << 5)
#define LCR_SB  		(0x1 << 6)
#define LCR_DLAB1 		(0x1 << 7)

// Masks for Line Status Reg. (LSR)

#define LSR_DR	 		(0x1 << 0)
#define LSR_OE	 		(0x1 << 1)
#define LSR_PE	 		(0x1 << 2)
#define LSR_FE	 		(0x1 << 3)
#define LSR_BI	 		(0x1 << 4)
#define LSR_TDRQ 		(0x1 << 5)
#define LSR_TEMT 		(0x1 << 6)
#define LSR_FIFOE	 	(0x1 << 7)

// Masks for Modem Control Reg.

#define MCR_DTR	 		(0x1 << 0)
#define MCR_RTS	 		(0x1 << 1)
#define MCR_OUT1 		(0x1 << 2)
#define MCR_OUT2 		(0x1 << 3)
#define MCR_LOOP 		(0x1 << 4)

// Masks for Modem Status Reg. (MSR)

#define MSR_DCTS 		(0x1 << 0)
#define MSR_DDSR 		(0x1 << 1)
#define MSR_PE	 		(0x1 << 2)
#define MSR_FE	 		(0x1 << 3)
#define MSR_BI	 		(0x1 << 4)
#define MSR_TDRQ 		(0x1 << 5)
#define MSR_TEMT 		(0x1 << 6)
#define MSR_FIFOE	 	(0x1 << 7)

// Masks for Infrared Selection Reg. (ISR)

#define ISR_XMITIR 		(0x1 << 0)
#define ISR_RCVEIR 		(0x1 << 1)
#define ISR_XMODE 		(0x1 << 2)
#define ISR_TXPL 		(0x1 << 3)
#define ISR_RXPL 		(0x1 << 4)

// Minimum values of divisors programmed in divisor latch reg.

#define FFDIVISOR_MIN	4				// FFUART divisor
#define BTDIVISOR_MIN	1				// BTUART divisor
#define STDIVISOR_MIN	4				// STUART divisor

#define RETRY			10

#define	NUM_BUF_DEFAULT		2	
#define	BUFF_SIZE_DEFAULT	64	
#define	XFER_LEN_DEFAULT	128

#define FFUARTREG_BASE	(0x40100000)	// FFUART Base Register Location
#define BTUARTREG_BASE	(0x40200000)	// BTUART Base Register Location
#define STUARTREG_BASE	(0x40700000)	// STUART Base Register Location

typedef struct bufInfo_S {
	char * buf;
	void * param;
	int len;
} bufInfo_T;

typedef enum UartLoopbackMode_E
{
    UartLoopbackOff = 0,
    UartLoopbackOn = 1
} UartLoopbackMode_T;

typedef enum UartType_E
{
	FFUartType = 0,
	BTUartType,
	STUartType,
	SystemUart = 0xff00
} UartType_T;



#endif //__XSUART_REGS_H