xspwmregs.h

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/******************************************************************************
**
**  COPYRIGHT (C) 2000 Intel Corporation
**
**	FILENAME			:	XsPwmRegs.h
**  Reference FILENAME	:   xsPwm.h
**
**  PURPOSE:		This file containes the PWM's register definitions		       
**
**  LAST MODIFIED: 12/20/2000
******************************************************************************/

#ifndef __XSPWM_REG_H
#define __XSPWM_REG_H

/*
************************************************************************************
*                             Register Physical Addresses 
************************************************************************************
*/
#define CTRL_IDX	0	
#define DUTY_IDX	1
#define PERVAL_IDX	2

#define PWM0REG_PHY_BASE_ADDR	(0x40B00000)
#define PWM1REG_PHY_BASE_ADDR	(0x40C00000)
#define PWM0_CTRL_ADDR		(PWM0REG_PHY_BASE_ADDR + 0x0)
#define PWM0_DUTY_ADDR		(PWM0REG_PHY_BASE_ADDR + 0x4)
#define PWM0_PERVAL_ADDR	(PWM0REG_PHY_BASE_ADDR + 0x8)
#define PWM1_CTRL_ADDR		(PWM1REG_PHY_BASE_ADDR + 0x0)
#define PWM1_DUTY_ADDR		(PWM1REG_PHY_BASE_ADDR + 0x4)
#define PWM1_PERVAL_ADDR	(PWM1REG_PHY_BASE_ADDR + 0x8)

#define PWM_CTRL_ADDR(chan)		(PWM0_CTRL_ADDR + chan * 0x100000)
#define PWM_DUTY_ADDR(chan)		(PWM0_DUTY_ADDR + chan * 0x100000)
#define PWM_PERVAL_ADDR(chan)	(PWM0_PERVAL_ADDR + chan * 0x100000)

#define PWM0_CTRL	*(volatile unsigned int *)PWM0_CTRL_ADDR
#define PWM0_DUTY	*(volatile unsigned int *)PWM0_DUTY_ADDR
#define PWM0_PERVAL	*(volatile unsigned int *)PWM0_PERVAL_ADDR
#define PWM1_CTRL	*(volatile unsigned int *)PWM1_CTRL_ADDR
#define PWM1_DUTY	*(volatile unsigned int *)PWM1_DUTY_ADDR
#define PWM1_PERVAL	*(volatile unsigned int *)PWM1_PERVAL_ADDR

#define PWM_CTRL(chan)		*(volatile unsigned int *)(PWM_CTRL_ADDR(chan))
#define PWM_DUTY(chan)		*(volatile unsigned int *)(PWM_DUTY_ADDR(chan))
#define PWM_PERVAL(chan)	*(volatile unsigned int *)(PWM_PERVAL_ADDR(chan))
/*
************************************************************************************
*                             Bits and Length Definitions 
************************************************************************************
*/
// Note: 
//      - XX_OFS means the bit offset 
//	    - XX_SZ means the field length

#define	PWM_CTRL_PRESCALE_OFS	(0)
#define	PWM_CTRL_PRESCALE_SZ	(6)
#define	PWM_CTRL_SD_OFS			(6)

#define PWM_DUTY_DCYCLE_OFS		(0)
#define PWM_DUTY_DCYCLE_SZ		(10)
#define PWM_DUTY_FDCYCLE_OFS	(10)

#define PWM_PERVAL_PV_OFS		(0)
#define PWM_PERVAL_PV_SZ		(10)

/* PWM Control Registers (CTRL) definitions */
#define PWM_CTRL_MASK           0x7F
#define PWM_CTRL_PRESCALE_SHIFT 0
#define PWM_CTRL_PRESCALE_MASK  0x3F     /* Mask for accessing PRESCALE */
#define PWM_CTRL_PWM_SD     ( 0x1 << 6 ) /* Abrupt shutdown of PWM when
                                            processor transitions to
                                            Unit Stop Clk or Suspend */
// bit 8-31 reserved

/* PWM Duty Cycle Registers (DUTY) definitions */
#define PWM_DUTY_MASK           0x7FF
#define PWM_DUTY_DCYCLE_SHIFT   0
#define PWM_DUTY_DCYCLE_MASK    0x3FF         /* Mask for accessing DCYCLE */
#define PWM_DUTY_FDCYCLE        ( 0x1 << 10 ) /* PWM output is full duty
                                                 cycle. The DCYCLE setting
                                                 is ignored*/
// bits 11-31 reserved

/* PWM Period Registers (PERVAL) definitions */
#define PWM_PERVAL_SHIFT    0
#define PWM_PERVAL_MASK     0x3FF
// bits 10-31 reserved

/* Address of Cotulla Pulse Width Modulation registers */
#define PWM0_REG_BASE 0x40B00000
#define PWM1_REG_BASE 0x40C00000
#define PWM_CHANNEL_OFFSET  ( PWM1_REG_BASE - PWM0_REG_BASE )

typedef struct PwmCtrlRegsS
{
	unsigned int CTRL ;
	unsigned int DUTY ;
	unsigned int PERVAL ;
} PwmCtrlRegsT ;

typedef enum PwmDeviceE
{
	PWM0 = 0,
	PWM1
} PwmDeviceE;

#endif // __XSPWM_REG_H