xsicpdrv.h

usb 检验程序

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:   xsicp.h
**
**  PURPOSE:    This file defines types and masks to be used with
**              Infrared Communications Port (ICP) control registers.
**
**  LAST MODIFIED: 	02/21/01
**	EAS VERSION  :	2.0
******************************************************************************/

#ifndef __XSICP_DRV_H
#define __XSICP_DRV_H

/*
************************************************************************************
*							CONSTANTS 
************************************************************************************
*/

#ifdef ICP_GLOBALS
#define EXTRN
#else
#define EXTRN extern
#endif

// Masks for ICP Registers

// Infrared Comm Port Control Register 0 (ICCR0) definitions
#define ICP_ICCR0_ITR			( 0x1 << 0 ) // ICP unit enabled
#define ICP_ICCR0_LBM       	( 0x1 << 1 ) // This selects loopback mode of operation
#define ICP_ICCR0_TUS			( 0x1 << 2 ) // bit 2 slects FIFO underrun response
#define ICP_ICCR0_TXE			( 0x1 << 3 ) // bit 3 enables HSSP transmit logic
#define ICP_ICCR0_RXE			( 0x1 << 4 ) // bit 4 enables HSSP receive logic
#define ICP_ICCR0_RIE			( 0x1 << 5 ) // bit 5 disables/enables Rx FIFO interrupt
#define ICP_ICCR0_TIE			( 0x1 << 6 ) // bit 6 disables/enables Tx FIFO interrupt 
#define ICP_ICCR0_AME			( 0x1 << 7 ) // bit 7 disables/enables receiver address match function

// Infrared Comm Port Control Register 1 (ICCR1) definitions
#define ICP_ICCR1_MASK      	( 0xFF << 0 )// Use to mask reserved bits to zero when reading and writing ICCR1.

// Infrared Comm Port Control Register 2 (ICCR2) definitions
#define ICP_ICCR2_TRIG_SHIFT	0			 // These 2 bits control the FIFO trigger level
// Configure TRIG field so that service request is issued when:                                       
#define ICP_ICCR2_TRIG_8BYTES  	( 0x0 << ICP_ICCR2_TRIG_SHIFT ) // >=8 bytes
#define ICP_ICCR2_TRIG_16BYTES 	( 0x1 << ICP_ICCR2_TRIG_SHIFT ) // >=16 bytes
#define ICP_ICCR2_TRIG_32BYTES 	( 0x2 << ICP_ICCR2_TRIG_SHIFT ) // >=32 bytes

#define ICP_ICCR2_TXP			( 0x1 << 2 ) // Data output from ICP to Tx pin is not inverted
#define ICP_ICCR2_RXP			( 0x1 << 3 ) // Data input from Tx pin to ICP is not inverted

// Infrared Comm Port Data Register (ICDR) definitions
#define ICP_ICDR_MASK   		0xFF 		 // Use to mask bits 8-31 to zero

// Infrared Comm Port Status Register 0 (ICSR0) definitions
#define ICP_ICSR0_EIF			( 0x1 << 0 ) // End/Error in FIFO
#define ICP_ICSR0_TUR			( 0x1 << 1 ) // Transmit FIFO underrun
#define ICP_ICSR0_RAB			( 0x1 << 2 ) // Receiver abort detected
#define ICP_ICSR0_TFS			( 0x1 << 3 ) // Transmit FIFO service request
#define ICP_ICSR0_RFS			( 0x1 << 4 ) // Receiver FIFO service request
#define ICP_ICSR0_FRE			( 0x1 << 5 ) // Framing error

// Infrared Comm Port Status Register 1 (ICSR1) definitions
//  All bits in register ICSR1 are READ-ONLY
#define ICP_ICSR1_RSY			( 0x1 << 0 ) // Indicates IR is in sync
#define ICP_ICSR1_TBY			( 0x1 << 1 ) // Transmitter is transmitting	a frame
#define ICP_ICSR1_RNE			( 0x1 << 2 ) // Rx FIFO is not empty
#define ICP_ICSR1_TNF			( 0x1 << 3 ) // Tx FIFO is not full
#define ICP_ICSR1_EOF			( 0x1 << 4 ) // Value at bottom of RX FIFO is last byte
#define ICP_ICSR1_CRE			( 0x1 << 5 ) // CRC error occurred
#define ICP_ICSR1_ROR			( 0x1 << 6 ) // Rx FIFO overrun occurred

//ICP Base register
#define ICP_REGS_BASE			0x40800000

#define ICP_MATCH_ALL			0xff		// This is used to automatically generate match
											// of all incoming frames  
#define ICP_RETRY_LOOP			1000

#define	NUM_BUF_DEFAULT_ICP		2	
#define	BUFF_SIZE_DEFAULT_ICP	64	
#define	XFER_LEN_DEFAULT_ICP	128

/*																								  regsP->
************************************************************************************
*							DATA TYPES                
************************************************************************************
*/

// ICP Registers structure 
typedef struct IcpRegsS
{
	VUINT32 ICCR0;
	VUINT32	ICCR1;
	VUINT32	ICCR2;
	VUINT32	ICDR;
	VUINT32	reserved1;
	VUINT32	ICSR0;
	VUINT32	ICSR1;
} IcpRegsT;

// ICP configuration structures
// This structure is used by the hardware setup function 
// to configure ICP
typedef struct IcpCfgS 
{
	INT	loopback;				// The loopback mode is enabled, if this is set to one
	INT function;				// Selects Rx or Tx operation
	INT actionTxFIFOUnderrun;	// Abort on Tx FIFO underrun, if this is set to one
	INT RxIntEnable;			// Receive FIFO interrupt enabled, if this is set to one
	INT TxIntEnable;			// Transmit FIFO interrupt enabled, if this is set to one
	INT enableAddressMatch;		// Address match enabled, if this is set to one
	INT addressMatchValue;		// Address match value (0-255) 
	INT	RxFIFOTrgLevel;			// Rx FIFO trigger level: 0 - 8 bytes, 1 - 16 bytes, 2 - 32 bytes
	INT TxPinPolarity;			// Tx pin polarity is inverted, if this is set to zero   
	INT	RxPinPolarity;			// Rx pin polarity is inverted, if this is set to zero	 
} IcpCfgT;					

// DMA configuration structure
// Used to configure DMA to service ICP
typedef struct IcpDmaCfgS {
	UINT descNum;			// Number of the descriptors in the chain
	UINT bufferSize;		// buffer size for each of the descriptors, bytes
	UINT xferLength;		// Total length of the transfer, bytes
	UINT sourceName;		// Name of the source (see xsdma.h)
	UINT targetName;		// Name of the target (see xsdma.h)
	UINT priority;			// Channel's priority
} IcpDmaCfgT;

typedef enum IcpLoopE
{
    IcpLoopbackOff,
	IcpLoopbackOn
} IcpLoopT;

typedef enum IcpFunctionE
{
    IcpRxOperation,
	IcpTxOperation
} IcpFunctionT;


typedef enum IcpTxFIFOUnderunE
{
    IcpTxFIFOUnderunNoInt,
	IcpTxFIFOUnderunInt
} IcpTxFIFOUnderunT;

typedef enum IcpFIFOIntE
{
    IcpFIFOIntDisabled,
	IcpFIFOIntEnabled
} IcpFIFOIntT;

typedef enum IcpAddressMatchE
{
    IcpAddressMatchDisabled,
	IcpAddressMatchEnabled
} IcpAddressMatchT;

typedef enum IcpRxFIFOTrgLevelE
{
    IcpRxFIFOTrgLevel8,
    IcpRxFIFOTrgLevel16,
	IcpRxFIFOTrgLevel32
} IcpRxFIFOTrgLevelT;

typedef enum IcpPinPolarityE
{
    IcpPinPolarityInvert,
	IcpPinPolarityNonInvert
} IcpPinPolarityT;

typedef enum IcpDmaServiceE
{
    IcpDmaNotUsed,
	IcpUseDma
} IcpDmaServiceT;

typedef enum IcpStatusReg0BitsE
{
	IcpFifoErr,
	IcpTxFifoUnderRun,
	IcpRxAbort,
	IcpTxFifoServReq,
	IcpRxFifoServReq,
	IcpFramingError
} IcpStatusReg0BitsT;

typedef enum IcpStatusReg1BitsE
{
	IcpRecvSynchBit,
	IcpTxBusy,
	IcpRxNotEmpty,
	IcpTxNotFull,
	IcpEndFrame,
	IcpCrcError,
	IcpRxOverrun	
} IcpStatusReg1BitsT;

// DMA Interrupt status structure
typedef struct IcpDmaStatusS {
	INT busErrorIntCount;
	INT endIntCount;
	INT startIntCount;
	INT	stopIntCount;
} IcpDmaStatusT;

// Interrupt status structure
typedef struct IcpIntStatusS {
	INT endErrorIntCount;
	INT txUnderunIntCount;
	INT rxAbortIntCount;
	INT	frameErrorIntCount;
} IcpIntStatusT;

UINT32 XsIcpDrv_HWSetup(volatile IcpRegsT * regsP, IcpCfgT * cfgP);
int XsIcpDrv_loopbackIcp(volatile IcpRegsT * regsP, INT data);
void XsIcpDrv_writeIcp (volatile IcpRegsT * regsP, PCHAR txbufP, INT len);
int XsIcpDrv_readIcp (volatile IcpRegsT * regsP, PCHAR rxbufP, INT len, int timeOut);

#endif  /* __XSICP_DRV_H */