📄 xssspregs.h
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/******************************************************************************
**
** COPYRIGHT (C) 2000 Intel Corporation
**
** FILENAME : XsSspRegs.h
** Reference FILENAME : xssp.h
**
** PURPOSE: This file containes the SSP's register definitions
**
** LAST MODIFIED: 12/20/2000
******************************************************************************/
#ifndef __XS_SSP_REGS_H
#define __XS_SSP_REGS_H
/*
************************************************************************************
* Included headers
************************************************************************************
*/
/*
************************************************************************************
* Register Physical Addresses
************************************************************************************
*/
#define SSPREG_PHY_BASE_ADDR 0x41000000
#define SSP_SSCR0_ADDR (SSPREG_PHY_BASE_ADDR + 0x0) // SSP Control Register 0
#define SSP_SSCR1_ADDR (SSPREG_PHY_BASE_ADDR + 0x4) // SSP Control Register 1
#define SSP_SSSR_ADDR (SSPREG_PHY_BASE_ADDR + 0x8) // SSP Status Register
#define SSP_SSITR_ADDR (SSPREG_PHY_BASE_ADDR + 0xC) // SSP Interrupt Test Register
#define SSP_SSDR_ADDR (SSPREG_PHY_BASE_ADDR + 0x10) // SSP Data Write/Read Register
#define SSP_SSCR0 *(volatile unsigned int *)SSP_SSCR0_ADDR
#define SSP_SSCR1 *(volatile unsigned int *)SSP_SSCR1_ADDR
#define SSP_SSSR *(volatile unsigned int *)SSP_SSSR_ADDR
#define SSP_SSITR *(volatile unsigned int *)SSP_SSITR_ADDR
#define SSP_SSDR *(volatile unsigned int *)SSP_SSDR_ADDR
/*
************************************************************************************
* Bit Offset and Length Definition
************************************************************************************
*/
// SSP Control Register 0 (SSCR0) definitions
#define SSP_SSCR0_DSS_OFS 0
#define SSP_SSCR0_DSS_SZ 4
#define SSP_SSCR0_FRF_OFS 4
#define SSP_SSCR0_FRF_SZ 2
#define SSP_SSCR0_ECS_OFS 6
#define SSP_SSCR0_SSE_OFS 7
#define SSP_SSCR0_SCR_OFS 8
#define SSP_SSCR0_SCR_SZ 8
// SSP Control Register 1 (SSCR1) definitions
#define SSP_SSCR1_RIE_OFS (0) // Rx FIFO lvl int enabled
#define SSP_SSCR1_TIE_OFS (1) // Tx FIFO lvl int enabled
#define SSP_SSCR1_LBM_OFS (2) // Serial loopback enabled
#define SSP_SSCR1_SPO_OFS (3) // IDLE state of SSPSCLK is Hi
#define SSP_SSCR1_SPH_OFS (4) // SSPSCLK is inactive 1/2 cycle
// at sart of and onw cycle at end of frame
#define SSP_SSCR1_MWDS_OFS (5) // 16-bit command words
#define SSP_SSCR1_TFT_OFS (6) // Transmit FIFO interrupt threshold value
#define SSP_SSCR1_TFT_SZ (4)
#define SSP_SSCR1_RFT_OFS (10) // Receive FIFO interrupt threshold value
#define SSP_SSCR1_RFT_SZ (4)
// SSP Status Register (SSSR) definitions
#define SSP_SSSR_TNF_OFS (2) // Tx FIFO not full
#define SSP_SSSR_RNE_OFS (3) // Rx FIFO not empty
#define SSP_SSSR_BSY_OFS (4) // SSP is currently transmitting
#define SSP_SSSR_TFS_OFS (5) // Tx FIFO is at <= TFT Thresh
#define SSP_SSSR_RFS_OFS (6) // Rx FIFO is at >= RFT Thresh
#define SSP_SSSR_ROR_OFS (7) // Attempted write to full Rx FIFO
#define SSP_SSSR_TFL_OFS (8) // Use to read/clear Number of entries in Tx FIFO
#define SSP_SSSR_TFL_SZ (4)
#define SSP_SSSR_RFL_OFS (12) // Use to read/clear Number of entries in Rx FIFO
#define SSP_SSSR_RFL_SZ (4)
/*
************************************************************************************
* CONSTANTS
************************************************************************************
*/
#ifdef SSP_GLOBALS
#define EXTRN
#else
#define EXTRN extern
#endif
// Masks for SSP Registers
// SSP Control Register 0 (SSCR0) definitions
#define SSP_SSCR0_DSS_MASK 0xf // Use to read/clear the DSS field
#define SSP_SSCR0_DSS_4 ( 0x3 << 0 ) // 4-bit data
#define SSP_SSCR0_DSS_5 ( 0x4 << 0 ) // 5-bit data
#define SSP_SSCR0_DSS_6 ( 0x5 << 0 ) // 6-bit data
#define SSP_SSCR0_DSS_7 ( 0x6 << 0 ) // 7-bit data
#define SSP_SSCR0_DSS_8 ( 0x7 << 0 ) // 8-bit data
#define SSP_SSCR0_DSS_9 ( 0x8 << 0 ) // 9-bit data
#define SSP_SSCR0_DSS_10 ( 0x9 << 0 ) // 10-bit data
#define SSP_SSCR0_DSS_11 ( 0xa << 0 ) // 11-bit data
#define SSP_SSCR0_DSS_12 ( 0xb << 0 ) // 12-bit data
#define SSP_SSCR0_DSS_13 ( 0xc << 0 ) // 13-bit data
#define SSP_SSCR0_DSS_14 ( 0xd << 0 ) // 14-bit data
#define SSP_SSCR0_DSS_15 ( 0xe << 0 ) // 15-bit data
#define SSP_SSCR0_DSS_16 ( 0xf << 0 ) // 16-bit data
#define SSP_SSCR0_FRF_MASK 0x30 // Use to read/clear the FRF field
#define SSP_SSCR0_FRF_SPI ( 0x0 << 4 ) // Serial Peripheral Interface
#define SSP_SSCR0_FRF_SSP ( 0x1 << 4 ) // TI Sync. Serial Protocol
#define SSP_SSCR0_FRF_MICWIRE ( 0x2 << 4 ) // National Microwire
#define SSP_SSCR0_ECS ( 0x1 << 6 ) // External clock is used to create the SSP's SSPSCLK
#define SSP_SSCR0_SSE ( 0x1 << 7 ) // SSP operation enabled
#define SSP_SSCR0_SCR_MASK ( 0xff << 8 ) // Use to mask SCR value
#define SSP_SSCR0_SCR_SHIFT 8 // Use to shift SCR value
// SSP Control Register 1 (SSCR1) definitions
#define SSP_SSCR1_RIE ( 0x1 << 0 ) // Rx FIFO lvl int enabled
#define SSP_SSCR1_TIE ( 0x1 << 1 ) // Tx FIFO lvl int enabled
#define SSP_SSCR1_LBM ( 0x1 << 2 ) // Serial loopback enabled
#define SSP_SSCR1_SPO ( 0x1 << 3 ) // IDLE state of SSPSCLK is Hi
#define SSP_SSCR1_SPH ( 0x1 << 4 ) // SSPSCLK is inactive 1/2 cycle
// at sart of and onw cycle at end of frame
#define SSP_SSCR1_MWDS ( 0x1 << 5 ) // 16-bit command words
// Use the TFT mask and shift to set or clear
// the Transmit FIFO interrupt threshold value fields
#define SSP_SSCR1_TFT_SHFT 6
#define SSP_SSCR1_TFT_MASK ( 0xf << SSP_SSCR1_TFT_SHFT )
// Use the RFT mask and shift to set or clear
// the Receive FIFO interrupt threshold value fields
#define SSP_SSCR1_RFT_SHFT 10
#define SSP_SSCR1_RFT_MASK ( 0xf << SSP_SSCR1_RFT_SHFT )
#define SSP_SSCR1_EPWR ( 0x1 << 14 ) // FIFO W/R spec func enabled
#define SSP_SSCR1_STRF ( 0x1 << 15 ) // Rx FIFO selected for reads/writes throught the SSDR
// SSP Status Register (SSSR) definitions
#define SSP_SSSR_TNF ( 0x1 << 2 ) // Tx FIFO not full
#define SSP_SSSR_RNE ( 0x1 << 3 ) // Rx FIFO not empty
#define SSP_SSSR_BSY ( 0x1 << 4 ) // SSP is currently transmitting
#define SSP_SSSR_TFS ( 0x1 << 5 ) // Tx FIFO is at <= TFT Thresh
#define SSP_SSSR_RFS ( 0x1 << 6 ) // Rx FIFO is at >= RFT Thresh
#define SSP_SSSR_ROR ( 0x1 << 7 ) // Attempted write to full Rx FIFO
// Use the following for determining and manipulating Tx FIFO number of entries
#define SSP_SSSR_TFL_SHIFT 8
#define SSP_SSSR_TFL_MASK ( 0xf << SSP_SSSR_TFL_SHIFT ) // Use to read/clear
// Number of entries
// in Tx FIFO
// Use the following for determining and manipulating Rx FIFO number of entries
#define SSP_SSSR_RFL_SHIFT 12
#define SSP_SSSR_RFL_MASK ( 0xf << SSP_SSSR_RFL_SHIFT ) // Use to read/clear
// Number of entries
// in Rx FIFO
// SSP Interrupt Test Register (SSITR) definitions
#define SSP_SSITR_TTFS ( 0x1 << 5 ) // Test Tx FIFO service request
#define SSP_SSITR_TRFS ( 0x1 << 6 ) // Test Rx FIFO service request
#define SSP_SSITR_TROR ( 0x1 << 7 ) // Test Rx FIFO overrun
#define SSP_REG_BASE ( 0x41000000 )
#define NOT_USED 0
#define NUM_BUF_DEFAULT_SSP 2
#define BUFF_SIZE_DEFAULT_SSP 64
#define XFER_LEN_DEFAULT_SSP 128
/*
************************************************************************************
* DATA TYPES
************************************************************************************
*/
// SSP Registers structure
typedef struct SspRegS
{
unsigned int SSCR0; // SSP Control Register 0
unsigned int SSCR1; // SSP Control Register 1
unsigned int SSSR; // SSP Status Register
unsigned int SSITR; // SSP Interrupt Test Register
unsigned int SSDR; // SSP Data Write/Read Register
} SspRegT;
typedef enum SspFormatE
{
SspFormat_Spi,
SspFormat_Ssp,
SspFormat_Mwire
} SspFormatT;
typedef enum SspClockE
{
SspOnChipClock,
SspExtClock
} SspClockT;
typedef enum SspLoopModeE
{
SspLoopbackOff,
SspLoopbackOn
} SspLoopModeT;
typedef enum SspPolarSpiE
{
SpiPolarityLow,
SpiPolarityHigh
} SspPolarSpiT;
typedef enum SspPhaseSpiE
{
SpiPhaseOne,
SpiPhaseHalf
} SspPhaseSpiT;
typedef enum SspDataMwireE
{
MwireData8,
MwireData16
} SspDataMwireT;
typedef enum SspFIFOIntE
{
SspFIFOIntDisabled,
SspFIFOIntEnabled
} SspFIFOIntT;
typedef enum SspFIFOSpecE
{
SspFIFOSpecialDisabled,
SspFIFOSpecialEnabled
} SspFIFOSpecT;
typedef enum SspFIFOtypeE
{
SspTxFIFO,
SspRxFIFO
} SspFIFOtypeT;
// SSP configuration structure
// This structure is used by the hardware setup function
// to configure SSP
typedef struct SspCfgS
{
unsigned int dataSize; // Used to select data size (4 - 16 bit)
unsigned int frameFormat; // Used to select SPI(0), SSP(1) or Microwire interface(2)
unsigned int extClock; // An external clock is used, if this variable is set to one
unsigned int SspExtClockFreq;// If external clock is used this defines ext clock freq.
unsigned int bitRate; // Used to select bit rate (7200 - 1843200 bps)
unsigned int RxIntEnable; // Rx FIFO level interrupt is enabled, if this is set to one
unsigned int TxIntEnable; // Tx FIFO level interrupt is enabled, if this is set to one
unsigned int loopback; // The loopback mode is enabled, if this is set to one
unsigned int polaritySPI; // If SPI interface was selected, this is used to choose a polarity (0 - low)
unsigned int phaseSPI; // If SPI interface was selected, this is used to choose a phase (0 - one cycle at the start)
unsigned int dataMicroWire; // If Microwire interface was selected, this is used to choose the data (0 - 8 bit)
unsigned int thresholdTx; // Transmit FIFO treshold value minus one
unsigned int thresholdRx; // Receive FIFO treshold value minus one
unsigned int enableSpecial; // FIFO special function is enabled, if this is set to one
unsigned int selectFIFO; // If FIFO special function is enabled (0 - Tx FIFO), (1 - Rx FIFO)
} SspCfgT;
#endif //__XS_SSP_REGS_H⌨️ 快捷键说明
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