xsgpioregs.h

usb 检验程序

#define GAFR_AF50_OFS	4
#define GAFR_AF51_OFS	6
#define GAFR_AF52_OFS	8
#define GAFR_AF53_OFS	10
#define GAFR_AF54_OFS	12
#define GAFR_AF55_OFS	14
#define GAFR_AF56_OFS	16
#define GAFR_AF57_OFS	18
#define GAFR_AF58_OFS	20
#define GAFR_AF59_OFS	22
#define GAFR_AF60_OFS	24
#define GAFR_AF61_OFS	26
#define GAFR_AF62_OFS	28
#define GAFR_AF63_OFS	30

#define GAFR_AF64_OFS	0		// GAFR2_L
#define GAFR_AF65_OFS	2
#define GAFR_AF66_OFS	4
#define GAFR_AF67_OFS	6
#define GAFR_AF68_OFS	8
#define GAFR_AF69_OFS	10
#define GAFR_AF70_OFS	12
#define GAFR_AF71_OFS	14
#define GAFR_AF72_OFS	16
#define GAFR_AF73_OFS	18
#define GAFR_AF74_OFS	20
#define GAFR_AF75_OFS	22
#define GAFR_AF76_OFS	24
#define GAFR_AF77_OFS	26
#define GAFR_AF78_OFS	28
#define GAFR_AF79_OFS	30

#define GAFR_AF80_OFS	0		// GAFR2_U

#define GAFR_AF_SZ		2


/*
*******************************************************************************
    GPIO pin identifier definitions
*******************************************************************************
*/

typedef enum XsGpioIdE 
{
    XS_GPIO_ID_00     = 0,
    XS_GPIO_ID_01,
    XS_GPIO_ID_02,
    XS_GPIO_ID_03,
    XS_GPIO_ID_04,
    XS_GPIO_ID_05,
    XS_GPIO_ID_06,
    XS_GPIO_ID_07,
    XS_GPIO_ID_08,
    XS_GPIO_ID_09,
    XS_GPIO_ID_10,
    XS_GPIO_ID_11,
    XS_GPIO_ID_12,
    XS_GPIO_ID_13,
    XS_GPIO_ID_14,
    XS_GPIO_ID_15,
    XS_GPIO_ID_16,
    XS_GPIO_ID_17,
    XS_GPIO_ID_18,
    XS_GPIO_ID_19,
    XS_GPIO_ID_20,
    XS_GPIO_ID_21,
    XS_GPIO_ID_22,
    XS_GPIO_ID_23,
    XS_GPIO_ID_24,
    XS_GPIO_ID_25,
    XS_GPIO_ID_26,
    XS_GPIO_ID_27,
    XS_GPIO_ID_28,
    XS_GPIO_ID_29,
    XS_GPIO_ID_30,
    XS_GPIO_ID_31,
    XS_GPIO_ID_32,
    XS_GPIO_ID_33,
    XS_GPIO_ID_34,
    XS_GPIO_ID_35,
    XS_GPIO_ID_36,
    XS_GPIO_ID_37,
    XS_GPIO_ID_38,
    XS_GPIO_ID_39,
    XS_GPIO_ID_40,
    XS_GPIO_ID_41,
    XS_GPIO_ID_42,
    XS_GPIO_ID_43,
    XS_GPIO_ID_44,
    XS_GPIO_ID_45,
    XS_GPIO_ID_46,
    XS_GPIO_ID_47,
    XS_GPIO_ID_48,
    XS_GPIO_ID_49,
    XS_GPIO_ID_50,
    XS_GPIO_ID_51,
    XS_GPIO_ID_52,
    XS_GPIO_ID_53,
    XS_GPIO_ID_54,
    XS_GPIO_ID_55,
    XS_GPIO_ID_56,
    XS_GPIO_ID_57,
    XS_GPIO_ID_58,
    XS_GPIO_ID_59,
    XS_GPIO_ID_60,
    XS_GPIO_ID_61,
    XS_GPIO_ID_62,
    XS_GPIO_ID_63,
    XS_GPIO_ID_64,
    XS_GPIO_ID_65,
    XS_GPIO_ID_66,
    XS_GPIO_ID_67,
    XS_GPIO_ID_68,
    XS_GPIO_ID_69,
    XS_GPIO_ID_70,
    XS_GPIO_ID_71,
    XS_GPIO_ID_72,
    XS_GPIO_ID_73,
    XS_GPIO_ID_74,
    XS_GPIO_ID_75,
    XS_GPIO_ID_76,
    XS_GPIO_ID_77,
    XS_GPIO_ID_78,
    XS_GPIO_ID_79,
    XS_GPIO_ID_80,
    XS_GPIO_ID_MAX    = 80

} XsGpioIdT ; // end enum XsGpioIdE

// End GPIO pin identifier definitions


// Some aliases

#define XS_GPIO_ID_ICPSTUART_RX     XS_GPIO_ID_46
#define XS_GPIO_ID_ICPSTUART_TX     XS_GPIO_ID_47
#define XS_GPIO_ID_SSP_EXTCLK       XS_GPIO_ID_27

/*
************************************************************************************
*                            DATA TYPES 
************************************************************************************
*/
typedef struct XsGpioRegsS
{                       	// Interrupt Controller Reg usage

    unsigned int GPLR0;		// GPLR_x, _y, _z: pin-level
    unsigned int GPLR1;		
    unsigned int GPLR2;		
	unsigned int GPDR0;		// GPDR_x, _y, _z: pin direction
	unsigned int GPDR1;		
	unsigned int GPDR2;		
	unsigned int GPSR0;		// GPSR_x, _y, _z: pin output set
	unsigned int GPSR1;		
	unsigned int GPSR2;		
    unsigned int GPCR0;		// GPCR_x, _y, _z: pin output clear
    unsigned int GPCR1;
    unsigned int GPCR2;
	unsigned int GRER0;		// GRER_x, _y, _z: rising-edge detect
	unsigned int GRER1;
	unsigned int GRER2;
    unsigned int GFER0;		// GFER_x, _y, _z: falling-edge detect
    unsigned int GFER1;
    unsigned int GFER2;
    unsigned int GEDR0;		// GEDR_x, _y, _z: edge detect status
    unsigned int GEDR1;
    unsigned int GEDR2;
	unsigned int GAFR0_L;	// GAFR[0,1]_x, _y, _z: alternate function select
	unsigned int GAFR0_U;
	unsigned int GAFR1_L;
	unsigned int GAFR1_U;
	unsigned int GAFR2_L;
	unsigned int GAFR2_U;
}  XsGpioRegsT ;

/*
*******************************************************************************
    GPIO Pin Direction Definitions
        Note, only applies to pins selected as GPIO, not alternate function
*******************************************************************************
*/

typedef enum XsGpioDirE 
{
    XS_GPIO_DIR_MSK  =  1u,  // For construction of ANDing masks
    XS_GPIO_DIR_IN   =  0u,  // Zero bit level sets pin as input
    XS_GPIO_DIR_OUT  =  1u   // One bit level sets pin as output

} XsGpioDirT ; // end enum XsGpioDirE

// End GPIO Pin Direction Definitions

/*
*******************************************************************************
    GPIO Pin Level Definitions
        For use in specifying the level of an output pin.
*******************************************************************************
*/

typedef enum XsGpioPinLevelE 
{
    XS_GPIO_PIN_LEVEL_MSK   =  1u,  // For construction of ANDing masks
    XS_GPIO_PIN_LEVEL_0     =  0u,  // Set output level of pin to 0
    XS_GPIO_PIN_LEVEL_1     =  1u   // Set output level of pin to 1

} XsGpioPinLevelT ; // end enum XsGpioPinLevelE

// End GPIO Pin Level Definitions


/*
*******************************************************************************
    GPIO Edge Type Definitions for Edge Triggered Interrupts
        Applies only to GPI pins set to the input direction
*******************************************************************************
*/

typedef enum XsGpioIntTriggerEdgeE 
{
    XS_GPIO_INT_EDGE_MSK      =  1u,  // For construction of ANDing masks
    XS_GPIO_INT_NONE          =  0u,  // Do not interrupt on this pin.
    XS_GPIO_INT_RISING_EDGE   =  1u,  // Interrupt on rising edge only
    XS_GPIO_INT_FALLING_EDGE  =  2u,  // Interrupt on falling edge only
    XS_GPIO_INT_BOTH_EDGES    =  3u   // Interrupt on rising edge or falling edge

} XsGpioIntTriggerEdgeT ; // end enum XsGpioIntTriggerEdgelE

// End GPIO Edge Type Definitions for Edge Triggered Interrupts


/*
*******************************************************************************
    GPIO Alternate Function selection codes
*******************************************************************************
*/

typedef enum XsGpioAltFuncCodeE 
{
    XS_GPIO_ALT_FUNC_MSK    =  3u,  // For construction of ANDing masks
    XS_GPIO_ALT_FUNC_GPIO   =  0u,  // GPIO usage, no alternate function
    XS_GPIO_ALT_FUNC_1      =  1u,  // Alternate function 1 
    XS_GPIO_ALT_FUNC_2      =  2u,  // Alternate function 2 
    XS_GPIO_UNAVAILABLE     =  4u   // Internal use only.  Pin used by debugger
//  XS_GPIO_ALT_FUNC_3      =  3u   // Alternate function 3 (None in this processor)

} XsGpioAltFuncCodeT ; // end enum XsGpioAltFuncCodeE

// End GPIO Alternate Function selection codes


#endif // __xsgpioregs_h