fps200.h

指纹识别芯片fps200（富士通）在linux下的驱动程序（for arm7(ep7312) linux

/**
 * Title: fps200.h
 * Type: C_Head (*.h)
 * Description: the head file of fps200's driver in linux 2.4.x
 *        more: in current version, we just support 2.4.x, and so on, we don't use devfs
 * Copyright: Copyright (c) 2004
 * Company: NanKai University
 * author djws
 * version 1.0
 */


#ifndef _FPS200_H_
#define _FPS200_H_


#define ROW_NUM	300
#define COL_NUM	256

// address
//#define  FPS_INDEX     (*(volatile unsigned char *)FPS200_PHYS)
//#define  FPS_DATA      (*(volatile unsigned char *)(FPS200_PHYS+1))

///////////////
// Chip Operation

/*
The sensor array includes 256 columns and 300 rows of sensor plates. Associated with each column are two sample-andhold
circuits. A fingerprint image is sensed or captured one row at a time. This ?row capture? occurs in two phases. In
the first phase, the sensor plates of the selected row are pre-charged to the VDD voltage. During this pre-charge period,
an internal signal enables the first set of sample-and-hold circuits to store the pre-charged plate voltages of the row.
In the second phase, the row of sensor plates is discharged with a current source. The rate at which a cell is discharged is
proportional to the ?discharge current.? After a period of time (referred to as the ?discharge time?), an internal signal
enables the second set of sample-and-hold circuits to store the final plate voltages. The difference between the precharged
and discharged plate voltages is a measure of the capacitance of a sensor cell. After the row capture, the cells
within the row are ready to be digitized.
The sensitivity of the chip is adjusted by changing the discharge current and discharge time. The nominal value of the
current source is controlled by an external resistor connected between the ISET pin and ground. The current source is
controlled from the Discharge Current Register (DCR). The discharge time is controlled by the Discharge Time Register
(DTR).
*/

//////////////
// Pin Descriptions

// ISET:200k
// AIN:Pull this pin to ground, preferably with a resistor.
// FSET:56k
// XTAL1,XTAL2,circuit


//////////////
// function registers
// The function registers are accessed by indexed addressing. Write the index register to select a function register. Read or
// write the data register to access the contents of the function register.

// row column register#define FPS200_IOC_MAGIC 'k'
#define FPS200_IOCRESET _IO(FPS200_IOC_MAGIC)

#define  FPS_RAH   0x00	// row address register high, only bit 0 is used, which is RA[8]. write 0 to other bits
#define  FPS_RAL   0x01	// row address register lwo
#define  FPS_CAL   0x02	// column address register

// row column end register
#define  FPS_REH   0x03	// row address end register high, only bit 0 is used, which is RA[8]. write 0 to other bits
#define  FPS_REL   0x04	// row address end register low
#define  FPS_CEL   0x05	// column address end register

// discharge time register
// bit[7] reserved. write 0 to these bits
// bit[6:0] Sets the discharge time in oscillator clock periods.
#define  FPS_DTR   0x06
#define  FPS_DTR_TIME       0x70	/*     default:0x23 time:0x00-0x7f.the more the value the more light the color       */
					//DTR?DCR ==???
// discharge current register
// bit[7:5] reserved. write 0
// bit[4:0] sets the discharge current rate
#define  FPS_DCR   0x07
#define  FPS_DCR_CURRENT    0x6 /* default:0x01	discharge current value: 0x00-0x1f*/

// control register A
// Write this register to initiate image conversion. Read this register to read the A/D converter.
// Only one of GETSUB, GETIMG, or GETROW is write.
// set [7:4] bit as 0
// Rising Edge of WR- to First Data Valid 155 + n 156 + n Clock Cycles
// Rising Edge of RD- to Next Data Valid 6 7 Clock Cycles
#define  FPS_CTRLA 0x08
#define  FPS_CTRL_ASM_ARCH_EP7211_HA_GETSUB   0x04	// defined in row column register and row column end register
#define  FPS_CTRLA_GETIMG   0x02	// regardless of row column register and row column end register
#define  FPS_CTRLA_GETROW   0x01	// initiate a row capture, define in RAH and RAL.
#define  FPS_CTRLA_AINSEL	0x08	// A/D source is AIN pin instead of senor array

// control register B
// write 0 to bit[4]
#define  FPS_CTRLB 0x09
#define  FPS_CTRLB_MODE   0xC0		// bit[7:6] Reflects the state of the MODE[1:0] pins.
#define  FPS_CTRLB_RDY    0x20		// bit[5] 0 = A/D Conversion is in progress. 1 is idel
// WAIT- goes low if the
// A/D converter is read while an A/D conversion is in progress. WAIT- will remain low until the A/D conversion is completed.
#define  FPS_CTRLB_AFDEN  0x08		// 1:enable the automatic finger detection circuit.
#define  FPS_CTRLB_AUTOINCEN  0x04	// 1: Column addresses increment and another A/Dconversio is initiated after the A/D converter is read. The row address increments at the end of each column.
#define  FPS_CTRLB_XTALSEL	0x02	// when not in usb mode. 0 = Selects the internal 12 MHz multi-vibrator. 1 = Selects the XTAL1 pin.
#define  FPS_CTRLB_ENABLE  0x01		// 0: low-power state

// Control Register C
// bit[7:5] Programs the toggle rate of the P1 pin. all kind of toggle
// bit[4:2] Programs the toggle rate of the P0 pin.
// bit[2] when in one kind of toggle this bit reflag the pin P1, as is bit[1] does.
#define  FPS_CTRLC  0x0A

// status register a. the same as register a but read only
#define  FPS_SRA_ASM_ARCH_EP7211_H    0x0B
#define  FPS_SRA_GETSUB  0x04
#define  FPS_SRA_GETIMG  0x02
#define  FPS_SRA_GETROW  0x01
/*These three bit is set when CTRLA's correspond bit is set by software,
  cleared after the last byte is read*/

// programmable gain control register
// bit[7:4] reserved. bit[3:0] gain mode.
#define  FPS_PGC    0x0C
#define  FPS_PGC_VALUE 0x4//0xb				//???
/*
0000 = 1.00 (default gain)
0001 = 0.25
0010 = 0.50
0011 = 0.75
0100 = 1.00
0101 = 1.25
0110 = 1.50
0111 = 1.75
1000 = 4.00
1001 = 1.00
1010 = 2.00
1011 = 3.00
1100 = 4.00
1101 = 5.00
1110 = 6.00
1111 = 7.00*/

// interrupt control regsiter
// int 0: finger detect; int 1 external interrrput
#define  FPS_ICR    0x0D
#define  FPS_ICR_IP1_RISE    0x80	// external int polarity
#define  FPS_ICR_IP0_RISE    0x40	// finger int polarity
#define  FPS_ICR_IT1_LEVEL   0x20	// edage trigered int 1
#define  FPS_ICR_IT0_LEVEL   0x10	// edage trigered int 0
#define  FPS_ICR_IM1             0x08	//im 1 on int1 to isr
#define  FPS_ICR_IM0             0x04
#define  FPS_ICR_IE1             0x02	//int1 to isr but not interrupt
#define  FPS_ICR_IE0             0x01

// interrupt status regsiter
// bit[7:4] reserved. bit3 bit2 reflect int pins bit1 bit0 int flags
// write a 1 to int flags, clear the flags
#define  FPS_ISR    0x0E
#define  FPS_ISR_CLRINT  0x01

// Threshold Register
// This register controls the threshold at which a finger is detected by the automatic finger detection circuit.
// bit [7] reserved.
// bit [6:4] threshold voltage level
// bit [3:0] sharing capacitor size.
#define  FPS_THR    0x0F
#define  FPS_THR_THV  0x40
#define  FPS_THR_THC  0x09

// chip identification register high. content is 0x20
// cidl is 0x0a
#define  FPS_CIDH   0x10
#define  FPS_CIDL	0x11

// test mode register reserved
#define  FPS_TST    0x12

//////////////
// image read procedure
// Microprocessor Interface
/*
Get Whole Image
Write CTRLA with bit 1 set (GETIMG). This causes these events to happen: