📄 cvconst.h
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CV_IA64_AR89 = 3161,
CV_IA64_AR90 = 3162,
CV_IA64_AR91 = 3163,
CV_IA64_AR92 = 3164,
CV_IA64_AR93 = 3165,
CV_IA64_AR94 = 3166,
CV_IA64_AR95 = 3167,
CV_IA64_AR96 = 3168,
CV_IA64_AR97 = 3169,
CV_IA64_AR98 = 3170,
CV_IA64_AR99 = 3171,
CV_IA64_AR100 = 3172,
CV_IA64_AR101 = 3173,
CV_IA64_AR102 = 3174,
CV_IA64_AR103 = 3175,
CV_IA64_AR104 = 3176,
CV_IA64_AR105 = 3177,
CV_IA64_AR106 = 3178,
CV_IA64_AR107 = 3179,
CV_IA64_AR108 = 3180,
CV_IA64_AR109 = 3181,
CV_IA64_AR110 = 3182,
CV_IA64_AR111 = 3183,
CV_IA64_AR112 = 3184,
CV_IA64_AR113 = 3185,
CV_IA64_AR114 = 3186,
CV_IA64_AR115 = 3187,
CV_IA64_AR116 = 3188,
CV_IA64_AR117 = 3189,
CV_IA64_AR118 = 3190,
CV_IA64_AR119 = 3191,
CV_IA64_AR120 = 3192,
CV_IA64_AR121 = 3193,
CV_IA64_AR122 = 3194,
CV_IA64_AR123 = 3195,
CV_IA64_AR124 = 3196,
CV_IA64_AR125 = 3197,
CV_IA64_AR126 = 3198,
CV_IA64_AR127 = 3199,
// CPUID Registers
CV_IA64_CPUID0 = 3328,
CV_IA64_CPUID1 = 3329,
CV_IA64_CPUID2 = 3330,
CV_IA64_CPUID3 = 3331,
CV_IA64_CPUID4 = 3332,
// Control Registers
CV_IA64_ApDCR = 4096,
CV_IA64_ApITM = 4097,
CV_IA64_ApIVA = 4098,
CV_IA64_CR3 = 4099,
CV_IA64_CR4 = 4100,
CV_IA64_CR5 = 4101,
CV_IA64_CR6 = 4102,
CV_IA64_CR7 = 4103,
CV_IA64_ApPTA = 4104,
CV_IA64_ApGPTA = 4105,
CV_IA64_CR10 = 4106,
CV_IA64_CR11 = 4107,
CV_IA64_CR12 = 4108,
CV_IA64_CR13 = 4109,
CV_IA64_CR14 = 4110,
CV_IA64_CR15 = 4111,
CV_IA64_StIPSR = 4112,
CV_IA64_StISR = 4113,
CV_IA64_CR18 = 4114,
CV_IA64_StIIP = 4115,
CV_IA64_StIFA = 4116,
CV_IA64_StITIR = 4117,
CV_IA64_StIIPA = 4118,
CV_IA64_StIFS = 4119,
CV_IA64_StIIM = 4120,
CV_IA64_StIHA = 4121,
CV_IA64_CR26 = 4122,
CV_IA64_CR27 = 4123,
CV_IA64_CR28 = 4124,
CV_IA64_CR29 = 4125,
CV_IA64_CR30 = 4126,
CV_IA64_CR31 = 4127,
CV_IA64_CR32 = 4128,
CV_IA64_CR33 = 4129,
CV_IA64_CR34 = 4130,
CV_IA64_CR35 = 4131,
CV_IA64_CR36 = 4132,
CV_IA64_CR37 = 4133,
CV_IA64_CR38 = 4134,
CV_IA64_CR39 = 4135,
CV_IA64_CR40 = 4136,
CV_IA64_CR41 = 4137,
CV_IA64_CR42 = 4138,
CV_IA64_CR43 = 4139,
CV_IA64_CR44 = 4140,
CV_IA64_CR45 = 4141,
CV_IA64_CR46 = 4142,
CV_IA64_CR47 = 4143,
CV_IA64_CR48 = 4144,
CV_IA64_CR49 = 4145,
CV_IA64_CR50 = 4146,
CV_IA64_CR51 = 4147,
CV_IA64_CR52 = 4148,
CV_IA64_CR53 = 4149,
CV_IA64_CR54 = 4150,
CV_IA64_CR55 = 4151,
CV_IA64_CR56 = 4152,
CV_IA64_CR57 = 4153,
CV_IA64_CR58 = 4154,
CV_IA64_CR59 = 4155,
CV_IA64_CR60 = 4156,
CV_IA64_CR61 = 4157,
CV_IA64_CR62 = 4158,
CV_IA64_CR63 = 4159,
CV_IA64_SaLID = 4160,
CV_IA64_SaIVR = 4161,
CV_IA64_SaTPR = 4162,
CV_IA64_SaEOI = 4163,
CV_IA64_SaIRR0 = 4164,
CV_IA64_SaIRR1 = 4165,
CV_IA64_SaIRR2 = 4166,
CV_IA64_SaIRR3 = 4167,
CV_IA64_SaITV = 4168,
CV_IA64_SaPMV = 4169,
CV_IA64_SaCMCV = 4170,
CV_IA64_CR75 = 4171,
CV_IA64_CR76 = 4172,
CV_IA64_CR77 = 4173,
CV_IA64_CR78 = 4174,
CV_IA64_CR79 = 4175,
CV_IA64_SaLRR0 = 4176,
CV_IA64_SaLRR1 = 4177,
CV_IA64_CR82 = 4178,
CV_IA64_CR83 = 4179,
CV_IA64_CR84 = 4180,
CV_IA64_CR85 = 4181,
CV_IA64_CR86 = 4182,
CV_IA64_CR87 = 4183,
CV_IA64_CR88 = 4184,
CV_IA64_CR89 = 4185,
CV_IA64_CR90 = 4186,
CV_IA64_CR91 = 4187,
CV_IA64_CR92 = 4188,
CV_IA64_CR93 = 4189,
CV_IA64_CR94 = 4190,
CV_IA64_CR95 = 4191,
CV_IA64_CR96 = 4192,
CV_IA64_CR97 = 4193,
CV_IA64_CR98 = 4194,
CV_IA64_CR99 = 4195,
CV_IA64_CR100 = 4196,
CV_IA64_CR101 = 4197,
CV_IA64_CR102 = 4198,
CV_IA64_CR103 = 4199,
CV_IA64_CR104 = 4200,
CV_IA64_CR105 = 4201,
CV_IA64_CR106 = 4202,
CV_IA64_CR107 = 4203,
CV_IA64_CR108 = 4204,
CV_IA64_CR109 = 4205,
CV_IA64_CR110 = 4206,
CV_IA64_CR111 = 4207,
CV_IA64_CR112 = 4208,
CV_IA64_CR113 = 4209,
CV_IA64_CR114 = 4210,
CV_IA64_CR115 = 4211,
CV_IA64_CR116 = 4212,
CV_IA64_CR117 = 4213,
CV_IA64_CR118 = 4214,
CV_IA64_CR119 = 4215,
CV_IA64_CR120 = 4216,
CV_IA64_CR121 = 4217,
CV_IA64_CR122 = 4218,
CV_IA64_CR123 = 4219,
CV_IA64_CR124 = 4220,
CV_IA64_CR125 = 4221,
CV_IA64_CR126 = 4222,
CV_IA64_CR127 = 4223,
// Protection Key Registers
CV_IA64_Pkr0 = 5120,
CV_IA64_Pkr1 = 5121,
CV_IA64_Pkr2 = 5122,
CV_IA64_Pkr3 = 5123,
CV_IA64_Pkr4 = 5124,
CV_IA64_Pkr5 = 5125,
CV_IA64_Pkr6 = 5126,
CV_IA64_Pkr7 = 5127,
CV_IA64_Pkr8 = 5128,
CV_IA64_Pkr9 = 5129,
CV_IA64_Pkr10 = 5130,
CV_IA64_Pkr11 = 5131,
CV_IA64_Pkr12 = 5132,
CV_IA64_Pkr13 = 5133,
CV_IA64_Pkr14 = 5134,
CV_IA64_Pkr15 = 5135,
// Region Registers
CV_IA64_Rr0 = 6144,
CV_IA64_Rr1 = 6145,
CV_IA64_Rr2 = 6146,
CV_IA64_Rr3 = 6147,
CV_IA64_Rr4 = 6148,
CV_IA64_Rr5 = 6149,
CV_IA64_Rr6 = 6150,
CV_IA64_Rr7 = 6151,
// Performance Monitor Data Registers
CV_IA64_PFD0 = 7168,
CV_IA64_PFD1 = 7169,
CV_IA64_PFD2 = 7170,
CV_IA64_PFD3 = 7171,
CV_IA64_PFD4 = 7172,
CV_IA64_PFD5 = 7173,
CV_IA64_PFD6 = 7174,
CV_IA64_PFD7 = 7175,
// Performance Monitor Config Registers
CV_IA64_PFC0 = 7424,
CV_IA64_PFC1 = 7425,
CV_IA64_PFC2 = 7426,
CV_IA64_PFC3 = 7427,
CV_IA64_PFC4 = 7428,
CV_IA64_PFC5 = 7429,
CV_IA64_PFC6 = 7430,
CV_IA64_PFC7 = 7431,
// Instruction Translation Registers
CV_IA64_TrI0 = 8192,
CV_IA64_TrI1 = 8193,
CV_IA64_TrI2 = 8194,
CV_IA64_TrI3 = 8195,
CV_IA64_TrI4 = 8196,
CV_IA64_TrI5 = 8197,
CV_IA64_TrI6 = 8198,
CV_IA64_TrI7 = 8199,
// Data Translation Registers
CV_IA64_TrD0 = 8320,
CV_IA64_TrD1 = 8321,
CV_IA64_TrD2 = 8322,
CV_IA64_TrD3 = 8323,
CV_IA64_TrD4 = 8324,
CV_IA64_TrD5 = 8325,
CV_IA64_TrD6 = 8326,
CV_IA64_TrD7 = 8327,
// Instruction Breakpoint Registers
CV_IA64_DbI0 = 8448,
CV_IA64_DbI1 = 8449,
CV_IA64_DbI2 = 8450,
CV_IA64_DbI3 = 8451,
CV_IA64_DbI4 = 8452,
CV_IA64_DbI5 = 8453,
CV_IA64_DbI6 = 8454,
CV_IA64_DbI7 = 8455,
// Data Breakpoint Registers
CV_IA64_DbD0 = 8576,
CV_IA64_DbD1 = 8577,
CV_IA64_DbD2 = 8578,
CV_IA64_DbD3 = 8579,
CV_IA64_DbD4 = 8580,
CV_IA64_DbD5 = 8581,
CV_IA64_DbD6 = 8582,
CV_IA64_DbD7 = 8583,
//
// Register set for the TriCore processor.
//
CV_TRI_NOREG = CV_REG_NONE,
// General Purpose Data Registers
CV_TRI_D0 = 10,
CV_TRI_D1 = 11,
CV_TRI_D2 = 12,
CV_TRI_D3 = 13,
CV_TRI_D4 = 14,
CV_TRI_D5 = 15,
CV_TRI_D6 = 16,
CV_TRI_D7 = 17,
CV_TRI_D8 = 18,
CV_TRI_D9 = 19,
CV_TRI_D10 = 20,
CV_TRI_D11 = 21,
CV_TRI_D12 = 22,
CV_TRI_D13 = 23,
CV_TRI_D14 = 24,
CV_TRI_D15 = 25,
// General Purpose Address Registers
CV_TRI_A0 = 26,
CV_TRI_A1 = 27,
CV_TRI_A2 = 28,
CV_TRI_A3 = 29,
CV_TRI_A4 = 30,
CV_TRI_A5 = 31,
CV_TRI_A6 = 32,
CV_TRI_A7 = 33,
CV_TRI_A8 = 34,
CV_TRI_A9 = 35,
CV_TRI_A10 = 36,
CV_TRI_A11 = 37,
CV_TRI_A12 = 38,
CV_TRI_A13 = 39,
CV_TRI_A14 = 40,
CV_TRI_A15 = 41,
// Extended (64-bit) data registers
CV_TRI_E0 = 42,
CV_TRI_E2 = 43,
CV_TRI_E4 = 44,
CV_TRI_E6 = 45,
CV_TRI_E8 = 46,
CV_TRI_E10 = 47,
CV_TRI_E12 = 48,
CV_TRI_E14 = 49,
// Extended (64-bit) address registers
CV_TRI_EA0 = 50,
CV_TRI_EA2 = 51,
CV_TRI_EA4 = 52,
CV_TRI_EA6 = 53,
CV_TRI_EA8 = 54,
CV_TRI_EA10 = 55,
CV_TRI_EA12 = 56,
CV_TRI_EA14 = 57,
CV_TRI_PSW = 58,
CV_TRI_PCXI = 59,
CV_TRI_PC = 60,
CV_TRI_FCX = 61,
CV_TRI_LCX = 62,
CV_TRI_ISP = 63,
CV_TRI_ICR = 64,
CV_TRI_BIV = 65,
CV_TRI_BTV = 66,
CV_TRI_SYSCON = 67,
CV_TRI_DPRx_0 = 68,
CV_TRI_DPRx_1 = 69,
CV_TRI_DPRx_2 = 70,
CV_TRI_DPRx_3 = 71,
CV_TRI_CPRx_0 = 68,
CV_TRI_CPRx_1 = 69,
CV_TRI_CPRx_2 = 70,
CV_TRI_CPRx_3 = 71,
CV_TRI_DPMx_0 = 68,
CV_TRI_DPMx_1 = 69,
CV_TRI_DPMx_2 = 70,
CV_TRI_DPMx_3 = 71,
CV_TRI_CPMx_0 = 68,
CV_TRI_CPMx_1 = 69,
CV_TRI_CPMx_2 = 70,
CV_TRI_CPMx_3 = 71,
CV_TRI_DBGSSR = 72,
CV_TRI_EXEVT = 73,
CV_TRI_SWEVT = 74,
CV_TRI_CREVT = 75,
CV_TRI_TRnEVT = 76,
CV_TRI_MMUCON = 77,
CV_TRI_ASI = 78,
CV_TRI_TVA = 79,
CV_TRI_TPA = 80,
CV_TRI_TPX = 81,
CV_TRI_TFA = 82,
//
// Register set for the AM33 and related processors.
//
CV_AM33_NOREG = CV_REG_NONE,
// "Extended" (general purpose integer) registers
CV_AM33_E0 = 10,
CV_AM33_E1 = 11,
CV_AM33_E2 = 12,
CV_AM33_E3 = 13,
CV_AM33_E4 = 14,
CV_AM33_E5 = 15,
CV_AM33_E6 = 16,
CV_AM33_E7 = 17,
// Address registers
CV_AM33_A0 = 20,
CV_AM33_A1 = 21,
CV_AM33_A2 = 22,
CV_AM33_A3 = 23,
// Integer data registers
CV_AM33_D0 = 30,
CV_AM33_D1 = 31,
CV_AM33_D2 = 32,
CV_AM33_D3 = 33,
// (Single-precision) floating-point registers
CV_AM33_FS0 = 40,
CV_AM33_FS1 = 41,
CV_AM33_FS2 = 42,
CV_AM33_FS3 = 43,
CV_AM33_FS4 = 44,
CV_AM33_FS5 = 45,
CV_AM33_FS6 = 46,
CV_AM33_FS7 = 47,
CV_AM33_FS8 = 48,
CV_AM33_FS9 = 49,
CV_AM33_FS10 = 50,
CV_AM33_FS11 = 51,
CV_AM33_FS12 = 52,
CV_AM33_FS13 = 53,
CV_AM33_FS14 = 54,
CV_AM33_FS15 = 55,
CV_AM33_FS16 = 56,
CV_AM33_FS17 = 57,
CV_AM33_FS18 = 58,
CV_AM33_FS19 = 59,
CV_AM33_FS20 = 60,
CV_AM33_FS21 = 61,
CV_AM33_FS22 = 62,
CV_AM33_FS23 = 63,
CV_AM33_FS24 = 64,
CV_AM33_FS25 = 65,
CV_AM33_FS26 = 66,
CV_AM33_FS27 = 67,
CV_AM33_FS28 = 68,
CV_AM33_FS29 = 69,
CV_AM33_FS30 = 70,
CV_AM33_FS31 = 71,
// Special purpose registers
// Stack pointer
CV_AM33_SP = 80,
// Program counter
CV_AM33_PC = 81,
// Multiply-divide/accumulate registers
CV_AM33_MDR = 82,
CV_AM33_MDRQ = 83,
CV_AM33_MCRH = 84,
CV_AM33_MCRL = 85,
CV_AM33_MCVF = 86,
// CPU status words
CV_AM33_EPSW = 87,
CV_AM33_FPCR = 88,
// Loop buffer registers
CV_AM33_LIR = 89,
CV_AM33_LAR = 90,
//
// Register set for the Mitsubishi M32R
//
CV_M32R_NOREG = CV_REG_NONE,
CV_M32R_R0 = 10,
CV_M32R_R1 = 11,
CV_M32R_R2 = 12,
CV_M32R_R3 = 13,
CV_M32R_R4 = 14,
CV_M32R_R5 = 15,
CV_M32R_R6 = 16,
CV_M32R_R7 = 17,
CV_M32R_R8 = 18,
CV_M32R_R9 = 19,
CV_M32R_R10 = 20,
CV_M32R_R11 = 21,
CV_M32R_R12 = 22, // Gloabal Pointer, if used
CV_M32R_R13 = 23, // Frame Pointer, if allocated
CV_M32R_R14 = 24, // Link Register
CV_M32R_R15 = 25, // Stack Pointer
CV_M32R_PSW = 26, // Preocessor Status Register
CV_M32R_CBR = 27, // Condition Bit Register
CV_M32R_SPI = 28, // Interrupt Stack Pointer
CV_M32R_SPU = 29, // User Stack Pointer
CV_M32R_SPO = 30, // OS Stack Pointer
CV_M32R_BPC = 31, // Backup Program Counter
CV_M32R_ACHI = 32, // Accumulator High
CV_M32R_ACLO = 33, // Accumulator Low
CV_M32R_PC = 34, // Program Counter
} CV_HREG_e;
#endif
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