📄 cvconst.h
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//reserved 40
CV_R68_MMUSR030 = 41,
CV_R68_MMUSR = 42,
CV_R68_URP = 43,
CV_R68_DTT0 = 44,
CV_R68_DTT1 = 45,
CV_R68_ITT0 = 46,
CV_R68_ITT1 = 47,
//reserved 50
CV_R68_PSR = 51,
CV_R68_PCSR = 52,
CV_R68_VAL = 53,
CV_R68_CRP = 54,
CV_R68_SRP = 55,
CV_R68_DRP = 56,
CV_R68_TC = 57,
CV_R68_AC = 58,
CV_R68_SCC = 59,
CV_R68_CAL = 60,
CV_R68_TT0 = 61,
CV_R68_TT1 = 62,
//reserved 63
CV_R68_BAD0 = 64,
CV_R68_BAD1 = 65,
CV_R68_BAD2 = 66,
CV_R68_BAD3 = 67,
CV_R68_BAD4 = 68,
CV_R68_BAD5 = 69,
CV_R68_BAD6 = 70,
CV_R68_BAD7 = 71,
CV_R68_BAC0 = 72,
CV_R68_BAC1 = 73,
CV_R68_BAC2 = 74,
CV_R68_BAC3 = 75,
CV_R68_BAC4 = 76,
CV_R68_BAC5 = 77,
CV_R68_BAC6 = 78,
CV_R68_BAC7 = 79,
// Register set for the MIPS 4000
CV_M4_NOREG = CV_REG_NONE,
CV_M4_IntZERO = 10, /* CPU REGISTER */
CV_M4_IntAT = 11,
CV_M4_IntV0 = 12,
CV_M4_IntV1 = 13,
CV_M4_IntA0 = 14,
CV_M4_IntA1 = 15,
CV_M4_IntA2 = 16,
CV_M4_IntA3 = 17,
CV_M4_IntT0 = 18,
CV_M4_IntT1 = 19,
CV_M4_IntT2 = 20,
CV_M4_IntT3 = 21,
CV_M4_IntT4 = 22,
CV_M4_IntT5 = 23,
CV_M4_IntT6 = 24,
CV_M4_IntT7 = 25,
CV_M4_IntS0 = 26,
CV_M4_IntS1 = 27,
CV_M4_IntS2 = 28,
CV_M4_IntS3 = 29,
CV_M4_IntS4 = 30,
CV_M4_IntS5 = 31,
CV_M4_IntS6 = 32,
CV_M4_IntS7 = 33,
CV_M4_IntT8 = 34,
CV_M4_IntT9 = 35,
CV_M4_IntKT0 = 36,
CV_M4_IntKT1 = 37,
CV_M4_IntGP = 38,
CV_M4_IntSP = 39,
CV_M4_IntS8 = 40,
CV_M4_IntRA = 41,
CV_M4_IntLO = 42,
CV_M4_IntHI = 43,
CV_M4_Fir = 50,
CV_M4_Psr = 51,
CV_M4_FltF0 = 60, /* Floating point registers */
CV_M4_FltF1 = 61,
CV_M4_FltF2 = 62,
CV_M4_FltF3 = 63,
CV_M4_FltF4 = 64,
CV_M4_FltF5 = 65,
CV_M4_FltF6 = 66,
CV_M4_FltF7 = 67,
CV_M4_FltF8 = 68,
CV_M4_FltF9 = 69,
CV_M4_FltF10 = 70,
CV_M4_FltF11 = 71,
CV_M4_FltF12 = 72,
CV_M4_FltF13 = 73,
CV_M4_FltF14 = 74,
CV_M4_FltF15 = 75,
CV_M4_FltF16 = 76,
CV_M4_FltF17 = 77,
CV_M4_FltF18 = 78,
CV_M4_FltF19 = 79,
CV_M4_FltF20 = 80,
CV_M4_FltF21 = 81,
CV_M4_FltF22 = 82,
CV_M4_FltF23 = 83,
CV_M4_FltF24 = 84,
CV_M4_FltF25 = 85,
CV_M4_FltF26 = 86,
CV_M4_FltF27 = 87,
CV_M4_FltF28 = 88,
CV_M4_FltF29 = 89,
CV_M4_FltF30 = 90,
CV_M4_FltF31 = 91,
CV_M4_FltFsr = 92,
// Register set for the ALPHA AXP
CV_ALPHA_NOREG = CV_REG_NONE,
CV_ALPHA_FltF0 = 10, // Floating point registers
CV_ALPHA_FltF1 = 11,
CV_ALPHA_FltF2 = 12,
CV_ALPHA_FltF3 = 13,
CV_ALPHA_FltF4 = 14,
CV_ALPHA_FltF5 = 15,
CV_ALPHA_FltF6 = 16,
CV_ALPHA_FltF7 = 17,
CV_ALPHA_FltF8 = 18,
CV_ALPHA_FltF9 = 19,
CV_ALPHA_FltF10 = 20,
CV_ALPHA_FltF11 = 21,
CV_ALPHA_FltF12 = 22,
CV_ALPHA_FltF13 = 23,
CV_ALPHA_FltF14 = 24,
CV_ALPHA_FltF15 = 25,
CV_ALPHA_FltF16 = 26,
CV_ALPHA_FltF17 = 27,
CV_ALPHA_FltF18 = 28,
CV_ALPHA_FltF19 = 29,
CV_ALPHA_FltF20 = 30,
CV_ALPHA_FltF21 = 31,
CV_ALPHA_FltF22 = 32,
CV_ALPHA_FltF23 = 33,
CV_ALPHA_FltF24 = 34,
CV_ALPHA_FltF25 = 35,
CV_ALPHA_FltF26 = 36,
CV_ALPHA_FltF27 = 37,
CV_ALPHA_FltF28 = 38,
CV_ALPHA_FltF29 = 39,
CV_ALPHA_FltF30 = 40,
CV_ALPHA_FltF31 = 41,
CV_ALPHA_IntV0 = 42, // Integer registers
CV_ALPHA_IntT0 = 43,
CV_ALPHA_IntT1 = 44,
CV_ALPHA_IntT2 = 45,
CV_ALPHA_IntT3 = 46,
CV_ALPHA_IntT4 = 47,
CV_ALPHA_IntT5 = 48,
CV_ALPHA_IntT6 = 49,
CV_ALPHA_IntT7 = 50,
CV_ALPHA_IntS0 = 51,
CV_ALPHA_IntS1 = 52,
CV_ALPHA_IntS2 = 53,
CV_ALPHA_IntS3 = 54,
CV_ALPHA_IntS4 = 55,
CV_ALPHA_IntS5 = 56,
CV_ALPHA_IntFP = 57,
CV_ALPHA_IntA0 = 58,
CV_ALPHA_IntA1 = 59,
CV_ALPHA_IntA2 = 60,
CV_ALPHA_IntA3 = 61,
CV_ALPHA_IntA4 = 62,
CV_ALPHA_IntA5 = 63,
CV_ALPHA_IntT8 = 64,
CV_ALPHA_IntT9 = 65,
CV_ALPHA_IntT10 = 66,
CV_ALPHA_IntT11 = 67,
CV_ALPHA_IntRA = 68,
CV_ALPHA_IntT12 = 69,
CV_ALPHA_IntAT = 70,
CV_ALPHA_IntGP = 71,
CV_ALPHA_IntSP = 72,
CV_ALPHA_IntZERO = 73,
CV_ALPHA_Fpcr = 74, // Control registers
CV_ALPHA_Fir = 75,
CV_ALPHA_Psr = 76,
CV_ALPHA_FltFsr = 77,
CV_ALPHA_SoftFpcr = 78,
// Register Set for Motorola/IBM PowerPC
/*
** PowerPC General Registers ( User Level )
*/
CV_PPC_GPR0 = 1,
CV_PPC_GPR1 = 2,
CV_PPC_GPR2 = 3,
CV_PPC_GPR3 = 4,
CV_PPC_GPR4 = 5,
CV_PPC_GPR5 = 6,
CV_PPC_GPR6 = 7,
CV_PPC_GPR7 = 8,
CV_PPC_GPR8 = 9,
CV_PPC_GPR9 = 10,
CV_PPC_GPR10 = 11,
CV_PPC_GPR11 = 12,
CV_PPC_GPR12 = 13,
CV_PPC_GPR13 = 14,
CV_PPC_GPR14 = 15,
CV_PPC_GPR15 = 16,
CV_PPC_GPR16 = 17,
CV_PPC_GPR17 = 18,
CV_PPC_GPR18 = 19,
CV_PPC_GPR19 = 20,
CV_PPC_GPR20 = 21,
CV_PPC_GPR21 = 22,
CV_PPC_GPR22 = 23,
CV_PPC_GPR23 = 24,
CV_PPC_GPR24 = 25,
CV_PPC_GPR25 = 26,
CV_PPC_GPR26 = 27,
CV_PPC_GPR27 = 28,
CV_PPC_GPR28 = 29,
CV_PPC_GPR29 = 30,
CV_PPC_GPR30 = 31,
CV_PPC_GPR31 = 32,
/*
** PowerPC Condition Register ( User Level )
*/
CV_PPC_CR = 33,
CV_PPC_CR0 = 34,
CV_PPC_CR1 = 35,
CV_PPC_CR2 = 36,
CV_PPC_CR3 = 37,
CV_PPC_CR4 = 38,
CV_PPC_CR5 = 39,
CV_PPC_CR6 = 40,
CV_PPC_CR7 = 41,
/*
** PowerPC Floating Point Registers ( User Level )
*/
CV_PPC_FPR0 = 42,
CV_PPC_FPR1 = 43,
CV_PPC_FPR2 = 44,
CV_PPC_FPR3 = 45,
CV_PPC_FPR4 = 46,
CV_PPC_FPR5 = 47,
CV_PPC_FPR6 = 48,
CV_PPC_FPR7 = 49,
CV_PPC_FPR8 = 50,
CV_PPC_FPR9 = 51,
CV_PPC_FPR10 = 52,
CV_PPC_FPR11 = 53,
CV_PPC_FPR12 = 54,
CV_PPC_FPR13 = 55,
CV_PPC_FPR14 = 56,
CV_PPC_FPR15 = 57,
CV_PPC_FPR16 = 58,
CV_PPC_FPR17 = 59,
CV_PPC_FPR18 = 60,
CV_PPC_FPR19 = 61,
CV_PPC_FPR20 = 62,
CV_PPC_FPR21 = 63,
CV_PPC_FPR22 = 64,
CV_PPC_FPR23 = 65,
CV_PPC_FPR24 = 66,
CV_PPC_FPR25 = 67,
CV_PPC_FPR26 = 68,
CV_PPC_FPR27 = 69,
CV_PPC_FPR28 = 70,
CV_PPC_FPR29 = 71,
CV_PPC_FPR30 = 72,
CV_PPC_FPR31 = 73,
/*
** PowerPC Floating Point Status and Control Register ( User Level )
*/
CV_PPC_FPSCR = 74,
/*
** PowerPC Machine State Register ( Supervisor Level )
*/
CV_PPC_MSR = 75,
/*
** PowerPC Segment Registers ( Supervisor Level )
*/
CV_PPC_SR0 = 76,
CV_PPC_SR1 = 77,
CV_PPC_SR2 = 78,
CV_PPC_SR3 = 79,
CV_PPC_SR4 = 80,
CV_PPC_SR5 = 81,
CV_PPC_SR6 = 82,
CV_PPC_SR7 = 83,
CV_PPC_SR8 = 84,
CV_PPC_SR9 = 85,
CV_PPC_SR10 = 86,
CV_PPC_SR11 = 87,
CV_PPC_SR12 = 88,
CV_PPC_SR13 = 89,
CV_PPC_SR14 = 90,
CV_PPC_SR15 = 91,
/*
** For all of the special purpose registers add 100 to the SPR# that the
** Motorola/IBM documentation gives with the exception of any imaginary
** registers.
*/
/*
** PowerPC Special Purpose Registers ( User Level )
*/
CV_PPC_PC = 99, // PC (imaginary register)
CV_PPC_MQ = 100, // MPC601
CV_PPC_XER = 101,
CV_PPC_RTCU = 104, // MPC601
CV_PPC_RTCL = 105, // MPC601
CV_PPC_LR = 108,
CV_PPC_CTR = 109,
CV_PPC_COMPARE = 110, // part of XER (internal to the debugger only)
CV_PPC_COUNT = 111, // part of XER (internal to the debugger only)
/*
** PowerPC Special Purpose Registers ( Supervisor Level )
*/
CV_PPC_DSISR = 118,
CV_PPC_DAR = 119,
CV_PPC_DEC = 122,
CV_PPC_SDR1 = 125,
CV_PPC_SRR0 = 126,
CV_PPC_SRR1 = 127,
CV_PPC_SPRG0 = 372,
CV_PPC_SPRG1 = 373,
CV_PPC_SPRG2 = 374,
CV_PPC_SPRG3 = 375,
CV_PPC_ASR = 280, // 64-bit implementations only
CV_PPC_EAR = 382,
CV_PPC_PVR = 287,
CV_PPC_BAT0U = 628,
CV_PPC_BAT0L = 629,
CV_PPC_BAT1U = 630,
CV_PPC_BAT1L = 631,
CV_PPC_BAT2U = 632,
CV_PPC_BAT2L = 633,
CV_PPC_BAT3U = 634,
CV_PPC_BAT3L = 635,
CV_PPC_DBAT0U = 636,
CV_PPC_DBAT0L = 637,
CV_PPC_DBAT1U = 638,
CV_PPC_DBAT1L = 639,
CV_PPC_DBAT2U = 640,
CV_PPC_DBAT2L = 641,
CV_PPC_DBAT3U = 642,
CV_PPC_DBAT3L = 643,
/*
** PowerPC Special Purpose Registers Implementation Dependent ( Supervisor Level )
*/
/*
** Doesn't appear that IBM/Motorola has finished defining these.
*/
CV_PPC_PMR0 = 1044, // MPC620,
CV_PPC_PMR1 = 1045, // MPC620,
CV_PPC_PMR2 = 1046, // MPC620,
CV_PPC_PMR3 = 1047, // MPC620,
CV_PPC_PMR4 = 1048, // MPC620,
CV_PPC_PMR5 = 1049, // MPC620,
CV_PPC_PMR6 = 1050, // MPC620,
CV_PPC_PMR7 = 1051, // MPC620,
CV_PPC_PMR8 = 1052, // MPC620,
CV_PPC_PMR9 = 1053, // MPC620,
CV_PPC_PMR10 = 1054, // MPC620,
CV_PPC_PMR11 = 1055, // MPC620,
CV_PPC_PMR12 = 1056, // MPC620,
CV_PPC_PMR13 = 1057, // MPC620,
CV_PPC_PMR14 = 1058, // MPC620,
CV_PPC_PMR15 = 1059, // MPC620,
CV_PPC_DMISS = 1076, // MPC603
CV_PPC_DCMP = 1077, // MPC603
CV_PPC_HASH1 = 1078, // MPC603
CV_PPC_HASH2 = 1079, // MPC603
CV_PPC_IMISS = 1080, // MPC603
CV_PPC_ICMP = 1081, // MPC603
CV_PPC_RPA = 1082, // MPC603
CV_PPC_HID0 = 1108, // MPC601, MPC603, MPC620
CV_PPC_HID1 = 1109, // MPC601
CV_PPC_HID2 = 1110, // MPC601, MPC603, MPC620 ( IABR )
CV_PPC_HID3 = 1111, // Not Defined
CV_PPC_HID4 = 1112, // Not Defined
CV_PPC_HID5 = 1113, // MPC601, MPC604, MPC620 ( DABR )
CV_PPC_HID6 = 1114, // Not Defined
CV_PPC_HID7 = 1115, // Not Defined
CV_PPC_HID8 = 1116, // MPC620 ( BUSCSR )
CV_PPC_HID9 = 1117, // MPC620 ( L2CSR )
CV_PPC_HID10 = 1118, // Not Defined
CV_PPC_HID11 = 1119, // Not Defined
CV_PPC_HID12 = 1120, // Not Defined
CV_PPC_HID13 = 1121, // MPC604 ( HCR )
CV_PPC_HID14 = 1122, // Not Defined
CV_PPC_HID15 = 1123, // MPC601, MPC604, MPC620 ( PIR )
//
// JAVA VM registers
//
CV_JAVA_PC = 1,
//
// Register set for the Hitachi SH3
//
CV_SH3_NOREG = CV_REG_NONE,
CV_SH3_IntR0 = 10, // CPU REGISTER
CV_SH3_IntR1 = 11,
CV_SH3_IntR2 = 12,
CV_SH3_IntR3 = 13,
CV_SH3_IntR4 = 14,
CV_SH3_IntR5 = 15,
CV_SH3_IntR6 = 16,
CV_SH3_IntR7 = 17,
CV_SH3_IntR8 = 18,
CV_SH3_IntR9 = 19,
CV_SH3_IntR10 = 20,
CV_SH3_IntR11 = 21,
CV_SH3_IntR12 = 22,
CV_SH3_IntR13 = 23,
CV_SH3_IntFp = 24,
CV_SH3_IntSp = 25,
CV_SH3_Gbr = 38,
CV_SH3_Pr = 39,
CV_SH3_Mach = 40,
CV_SH3_Macl = 41,
CV_SH3_Pc = 50,
CV_SH3_Sr = 51,
CV_SH3_BarA = 60,
CV_SH3_BasrA = 61,
CV_SH3_BamrA = 62,
CV_SH3_BbrA = 63,
CV_SH3_BarB = 64,
CV_SH3_BasrB = 65,
CV_SH3_BamrB = 66,
CV_SH3_BbrB = 67,
CV_SH3_BdrB = 68,
CV_SH3_BdmrB = 69,
CV_SH3_Brcr = 70,
//
// Additional registers for Hitachi SH processors
//
CV_SH_Fpscr = 75, // floating point status/control register
CV_SH_Fpul = 76, // floating point communication register
CV_SH_FpR0 = 80, // Floating point registers
CV_SH_FpR1 = 81,
CV_SH_FpR2 = 82,
CV_SH_FpR3 = 83,
CV_SH_FpR4 = 84,
CV_SH_FpR5 = 85,
CV_SH_FpR6 = 86,
CV_SH_FpR7 = 87,
CV_SH_FpR8 = 88,
CV_SH_FpR9 = 89,
CV_SH_FpR10 = 90,
CV_SH_FpR11 = 91,
CV_SH_FpR12 = 92,
CV_SH_FpR13 = 93,
CV_SH_FpR14 = 94,
CV_SH_FpR15 = 95,
CV_SH_XFpR0 = 96,
CV_SH_XFpR1 = 97,
CV_SH_XFpR2 = 98,
CV_SH_XFpR3 = 99,
CV_SH_XFpR4 = 100,
CV_SH_XFpR5 = 101,
CV_SH_XFpR6 = 102,
CV_SH_XFpR7 = 103,
CV_SH_XFpR8 = 104,
CV_SH_XFpR9 = 105,
CV_SH_XFpR10 = 106,
CV_SH_XFpR11 = 107,
CV_SH_XFpR12 = 108,
CV_SH_XFpR13 = 109,
CV_SH_XFpR14 = 110,
CV_SH_XFpR15 = 111,
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