📄 cvconst.h
字号:
// cvconst.h - codeview constant definitions
//-----------------------------------------------------------------
//
// Copyright Microsoft Corporation. All Rights Reserved.
//
//---------------------------------------------------------------
#ifndef _CVCONST_H_
#define _CVCONST_H_
// Enumeration for function call type
typedef enum CV_call_e {
CV_CALL_NEAR_C = 0x00, // near right to left push, caller pops stack
CV_CALL_FAR_C = 0x01, // far right to left push, caller pops stack
CV_CALL_NEAR_PASCAL = 0x02, // near left to right push, callee pops stack
CV_CALL_FAR_PASCAL = 0x03, // far left to right push, callee pops stack
CV_CALL_NEAR_FAST = 0x04, // near left to right push with regs, callee pops stack
CV_CALL_FAR_FAST = 0x05, // far left to right push with regs, callee pops stack
CV_CALL_SKIPPED = 0x06, // skipped (unused) call index
CV_CALL_NEAR_STD = 0x07, // near standard call
CV_CALL_FAR_STD = 0x08, // far standard call
CV_CALL_NEAR_SYS = 0x09, // near sys call
CV_CALL_FAR_SYS = 0x0a, // far sys call
CV_CALL_THISCALL = 0x0b, // this call (this passed in register)
CV_CALL_MIPSCALL = 0x0c, // Mips call
CV_CALL_GENERIC = 0x0d, // Generic call sequence
CV_CALL_ALPHACALL = 0x0e, // Alpha call
CV_CALL_PPCCALL = 0x0f, // PPC call
CV_CALL_SHCALL = 0x10, // Hitachi SuperH call
CV_CALL_ARMCALL = 0x11, // ARM call
CV_CALL_AM33CALL = 0x12, // AM33 call
CV_CALL_TRICALL = 0x13, // TriCore Call
CV_CALL_SH5CALL = 0x14, // Hitachi SuperH-5 call
CV_CALL_M32RCALL = 0x15, // M32R Call
CV_CALL_RESERVED = 0x16 // first unused call enumeration
} CV_call_e;
// Values for the access protection of class attributes
typedef enum CV_access_e {
CV_private = 1,
CV_protected = 2,
CV_public = 3
} CV_access_e;
typedef enum THUNK_ORDINAL {
THUNK_ORDINAL_NOTYPE, // standard thunk
THUNK_ORDINAL_ADJUSTOR, // "this" adjustor thunk
THUNK_ORDINAL_VCALL, // virtual call thunk
THUNK_ORDINAL_PCODE, // pcode thunk
THUNK_ORDINAL_LOAD, // thunk which loads the address to jump to
// via unknown means...
// trampoline thunk ordinals - only for use in Trampoline thunk symbols
THUNK_ORDINAL_TRAMP_INCREMENTAL,
THUNK_ORDINAL_TRAMP_BRANCHISLAND,
} THUNK_ORDINAL;
enum CV_SourceChksum_t {
CHKSUM_TYPE_NONE = 0, // indicates no checksum is available
CHKSUM_TYPE_MD5
};
//
// DIA enums
//
enum SymTagEnum
{
SymTagNull,
SymTagExe,
SymTagCompiland,
SymTagCompilandDetails,
SymTagCompilandEnv,
SymTagFunction,
SymTagBlock,
SymTagData,
SymTagReserved,
SymTagLabel,
SymTagPublicSymbol,
SymTagUDT,
SymTagEnum,
SymTagFunctionType,
SymTagPointerType,
SymTagArrayType,
SymTagBaseType,
SymTagTypedef,
SymTagBaseClass,
SymTagFriend,
SymTagFunctionArgType,
SymTagFuncDebugStart,
SymTagFuncDebugEnd,
SymTagUsingNamespace,
SymTagVTableShape,
SymTagVTable,
SymTagCustom,
SymTagThunk,
SymTagCustomType,
SymTagManagedType,
SymTagDimension,
SymTagMax
};
enum LocationType
{
LocIsNull,
LocIsStatic,
LocIsTLS,
LocIsRegRel,
LocIsThisRel,
LocIsEnregistered,
LocIsBitField,
LocIsSlot,
LocIsIlRel,
LocInMetaData,
LocIsConstant,
LocTypeMax
};
enum DataKind
{
DataIsUnknown,
DataIsLocal,
DataIsStaticLocal,
DataIsParam,
DataIsObjectPtr,
DataIsFileStatic,
DataIsGlobal,
DataIsMember,
DataIsStaticMember,
DataIsConstant
};
enum BasicType
{
btNoType = 0,
btVoid = 1,
btChar = 2,
btWChar = 3,
btInt = 6,
btUInt = 7,
btFloat = 8,
btBCD = 9,
btBool = 10,
btCurrency = 25,
btDate = 26,
btVariant = 27,
btComplex = 28,
btBit = 29,
btBSTR = 30,
btHresult = 31
};
// enum describing the compile flag source language
typedef enum CV_CFL_LANG {
CV_CFL_C = 0x00,
CV_CFL_CXX = 0x01,
CV_CFL_FORTRAN = 0x02,
CV_CFL_MASM = 0x03,
CV_CFL_PASCAL = 0x04,
CV_CFL_BASIC = 0x05,
CV_CFL_COBOL = 0x06,
CV_CFL_LINK = 0x07,
CV_CFL_CVTRES = 0x08,
CV_CFL_CVTPGD = 0x09,
} CV_CFL_LANG;
// enum describing target processor
typedef enum CV_CPU_TYPE_e {
CV_CFL_8080 = 0x00,
CV_CFL_8086 = 0x01,
CV_CFL_80286 = 0x02,
CV_CFL_80386 = 0x03,
CV_CFL_80486 = 0x04,
CV_CFL_PENTIUM = 0x05,
CV_CFL_PENTIUMII = 0x06,
CV_CFL_PENTIUMPRO = CV_CFL_PENTIUMII,
CV_CFL_PENTIUMIII = 0x07,
CV_CFL_MIPS = 0x10,
CV_CFL_MIPSR4000 = CV_CFL_MIPS, // don't break current code
CV_CFL_MIPS16 = 0x11,
CV_CFL_MIPS32 = 0x12,
CV_CFL_MIPS64 = 0x13,
CV_CFL_MIPSI = 0x14,
CV_CFL_MIPSII = 0x15,
CV_CFL_MIPSIII = 0x16,
CV_CFL_MIPSIV = 0x17,
CV_CFL_MIPSV = 0x18,
CV_CFL_M68000 = 0x20,
CV_CFL_M68010 = 0x21,
CV_CFL_M68020 = 0x22,
CV_CFL_M68030 = 0x23,
CV_CFL_M68040 = 0x24,
CV_CFL_ALPHA = 0x30,
CV_CFL_ALPHA_21064 = 0x30,
CV_CFL_ALPHA_21164 = 0x31,
CV_CFL_ALPHA_21164A = 0x32,
CV_CFL_ALPHA_21264 = 0x33,
CV_CFL_ALPHA_21364 = 0x34,
CV_CFL_PPC601 = 0x40,
CV_CFL_PPC603 = 0x41,
CV_CFL_PPC604 = 0x42,
CV_CFL_PPC620 = 0x43,
CV_CFL_PPCFP = 0x44,
CV_CFL_SH3 = 0x50,
CV_CFL_SH3E = 0x51,
CV_CFL_SH3DSP = 0x52,
CV_CFL_SH4 = 0x53,
CV_CFL_SHMEDIA = 0x54,
CV_CFL_ARM3 = 0x60,
CV_CFL_ARM4 = 0x61,
CV_CFL_ARM4T = 0x62,
CV_CFL_ARM5 = 0x63,
CV_CFL_ARM5T = 0x64,
CV_CFL_OMNI = 0x70,
CV_CFL_IA64 = 0x80,
CV_CFL_IA64_1 = 0x80,
CV_CFL_IA64_2 = 0x81,
CV_CFL_CEE = 0x90,
CV_CFL_AM33 = 0xA0,
CV_CFL_M32R = 0xB0,
CV_CFL_TRICORE = 0xC0,
CV_CFL_RESERVED1 = 0xD0,
} CV_CPU_TYPE_e;
typedef enum CV_HREG_e {
// Register subset shared by all processor types,
// must not overlap with any of the ranges below, hence the high values
CV_ALLREG_ERR = 30000,
CV_ALLREG_TEB = 30001,
CV_ALLREG_TIMER = 30002,
CV_ALLREG_EFAD1 = 30003,
CV_ALLREG_EFAD2 = 30004,
CV_ALLREG_EFAD3 = 30005,
CV_ALLREG_VFRAME= 30006,
CV_ALLREG_HANDLE= 30007,
CV_ALLREG_PARAMS= 30008,
CV_ALLREG_LOCALS= 30009,
// Register set for the Intel 80x86 and ix86 processor series
// (plus PCODE registers)
CV_REG_NONE = 0,
CV_REG_AL = 1,
CV_REG_CL = 2,
CV_REG_DL = 3,
CV_REG_BL = 4,
CV_REG_AH = 5,
CV_REG_CH = 6,
CV_REG_DH = 7,
CV_REG_BH = 8,
CV_REG_AX = 9,
CV_REG_CX = 10,
CV_REG_DX = 11,
CV_REG_BX = 12,
CV_REG_SP = 13,
CV_REG_BP = 14,
CV_REG_SI = 15,
CV_REG_DI = 16,
CV_REG_EAX = 17,
CV_REG_ECX = 18,
CV_REG_EDX = 19,
CV_REG_EBX = 20,
CV_REG_ESP = 21,
CV_REG_EBP = 22,
CV_REG_ESI = 23,
CV_REG_EDI = 24,
CV_REG_ES = 25,
CV_REG_CS = 26,
CV_REG_SS = 27,
CV_REG_DS = 28,
CV_REG_FS = 29,
CV_REG_GS = 30,
CV_REG_IP = 31,
CV_REG_FLAGS = 32,
CV_REG_EIP = 33,
CV_REG_EFLAGS = 34,
CV_REG_TEMP = 40, // PCODE Temp
CV_REG_TEMPH = 41, // PCODE TempH
CV_REG_QUOTE = 42, // PCODE Quote
CV_REG_PCDR3 = 43, // PCODE reserved
CV_REG_PCDR4 = 44, // PCODE reserved
CV_REG_PCDR5 = 45, // PCODE reserved
CV_REG_PCDR6 = 46, // PCODE reserved
CV_REG_PCDR7 = 47, // PCODE reserved
CV_REG_CR0 = 80, // CR0 -- control registers
CV_REG_CR1 = 81,
CV_REG_CR2 = 82,
CV_REG_CR3 = 83,
CV_REG_CR4 = 84, // Pentium
CV_REG_DR0 = 90, // Debug register
CV_REG_DR1 = 91,
CV_REG_DR2 = 92,
CV_REG_DR3 = 93,
CV_REG_DR4 = 94,
CV_REG_DR5 = 95,
CV_REG_DR6 = 96,
CV_REG_DR7 = 97,
CV_REG_GDTR = 110,
CV_REG_GDTL = 111,
CV_REG_IDTR = 112,
CV_REG_IDTL = 113,
CV_REG_LDTR = 114,
CV_REG_TR = 115,
CV_REG_PSEUDO1 = 116,
CV_REG_PSEUDO2 = 117,
CV_REG_PSEUDO3 = 118,
CV_REG_PSEUDO4 = 119,
CV_REG_PSEUDO5 = 120,
CV_REG_PSEUDO6 = 121,
CV_REG_PSEUDO7 = 122,
CV_REG_PSEUDO8 = 123,
CV_REG_PSEUDO9 = 124,
CV_REG_ST0 = 128,
CV_REG_ST1 = 129,
CV_REG_ST2 = 130,
CV_REG_ST3 = 131,
CV_REG_ST4 = 132,
CV_REG_ST5 = 133,
CV_REG_ST6 = 134,
CV_REG_ST7 = 135,
CV_REG_CTRL = 136,
CV_REG_STAT = 137,
CV_REG_TAG = 138,
CV_REG_FPIP = 139,
CV_REG_FPCS = 140,
CV_REG_FPDO = 141,
CV_REG_FPDS = 142,
CV_REG_ISEM = 143,
CV_REG_FPEIP = 144,
CV_REG_FPEDO = 145,
CV_REG_MM0 = 146,
CV_REG_MM1 = 147,
CV_REG_MM2 = 148,
CV_REG_MM3 = 149,
CV_REG_MM4 = 150,
CV_REG_MM5 = 151,
CV_REG_MM6 = 152,
CV_REG_MM7 = 153,
CV_REG_XMM0 = 154, // KATMAI registers
CV_REG_XMM1 = 155,
CV_REG_XMM2 = 156,
CV_REG_XMM3 = 157,
CV_REG_XMM4 = 158,
CV_REG_XMM5 = 159,
CV_REG_XMM6 = 160,
CV_REG_XMM7 = 161,
CV_REG_XMM00 = 162, // KATMAI sub-registers
CV_REG_XMM01 = 163,
CV_REG_XMM02 = 164,
CV_REG_XMM03 = 165,
CV_REG_XMM10 = 166,
CV_REG_XMM11 = 167,
CV_REG_XMM12 = 168,
CV_REG_XMM13 = 169,
CV_REG_XMM20 = 170,
CV_REG_XMM21 = 171,
CV_REG_XMM22 = 172,
CV_REG_XMM23 = 173,
CV_REG_XMM30 = 174,
CV_REG_XMM31 = 175,
CV_REG_XMM32 = 176,
CV_REG_XMM33 = 177,
CV_REG_XMM40 = 178,
CV_REG_XMM41 = 179,
CV_REG_XMM42 = 180,
CV_REG_XMM43 = 181,
CV_REG_XMM50 = 182,
CV_REG_XMM51 = 183,
CV_REG_XMM52 = 184,
CV_REG_XMM53 = 185,
CV_REG_XMM60 = 186,
CV_REG_XMM61 = 187,
CV_REG_XMM62 = 188,
CV_REG_XMM63 = 189,
CV_REG_XMM70 = 190,
CV_REG_XMM71 = 191,
CV_REG_XMM72 = 192,
CV_REG_XMM73 = 193,
CV_REG_XMM0L = 194,
CV_REG_XMM1L = 195,
CV_REG_XMM2L = 196,
CV_REG_XMM3L = 197,
CV_REG_XMM4L = 198,
CV_REG_XMM5L = 199,
CV_REG_XMM6L = 200,
CV_REG_XMM7L = 201,
CV_REG_XMM0H = 202,
CV_REG_XMM1H = 203,
CV_REG_XMM2H = 204,
CV_REG_XMM3H = 205,
CV_REG_XMM4H = 206,
CV_REG_XMM5H = 207,
CV_REG_XMM6H = 208,
CV_REG_XMM7H = 209,
CV_REG_MXCSR = 211, // XMM status register
CV_REG_EDXEAX = 212, // EDX:EAX pair
CV_REG_EMM0L = 220, // XMM sub-registers (WNI integer)
CV_REG_EMM1L = 221,
CV_REG_EMM2L = 222,
CV_REG_EMM3L = 223,
CV_REG_EMM4L = 224,
CV_REG_EMM5L = 225,
CV_REG_EMM6L = 226,
CV_REG_EMM7L = 227,
CV_REG_EMM0H = 228,
CV_REG_EMM1H = 229,
CV_REG_EMM2H = 230,
CV_REG_EMM3H = 231,
CV_REG_EMM4H = 232,
CV_REG_EMM5H = 233,
CV_REG_EMM6H = 234,
CV_REG_EMM7H = 235,
// do not change the order of these regs, first one must be even too
CV_REG_MM00 = 236,
CV_REG_MM01 = 237,
CV_REG_MM10 = 238,
CV_REG_MM11 = 239,
CV_REG_MM20 = 240,
CV_REG_MM21 = 241,
CV_REG_MM30 = 242,
CV_REG_MM31 = 243,
CV_REG_MM40 = 244,
CV_REG_MM41 = 245,
CV_REG_MM50 = 246,
CV_REG_MM51 = 247,
CV_REG_MM60 = 248,
CV_REG_MM61 = 249,
CV_REG_MM70 = 250,
CV_REG_MM71 = 251,
// registers for the 68K processors
CV_R68_D0 = 0,
CV_R68_D1 = 1,
CV_R68_D2 = 2,
CV_R68_D3 = 3,
CV_R68_D4 = 4,
CV_R68_D5 = 5,
CV_R68_D6 = 6,
CV_R68_D7 = 7,
CV_R68_A0 = 8,
CV_R68_A1 = 9,
CV_R68_A2 = 10,
CV_R68_A3 = 11,
CV_R68_A4 = 12,
CV_R68_A5 = 13,
CV_R68_A6 = 14,
CV_R68_A7 = 15,
CV_R68_CCR = 16,
CV_R68_SR = 17,
CV_R68_USP = 18,
CV_R68_MSP = 19,
CV_R68_SFC = 20,
CV_R68_DFC = 21,
CV_R68_CACR = 22,
CV_R68_VBR = 23,
CV_R68_CAAR = 24,
CV_R68_ISP = 25,
CV_R68_PC = 26,
//reserved 27
CV_R68_FPCR = 28,
CV_R68_FPSR = 29,
CV_R68_FPIAR = 30,
//reserved 31
CV_R68_FP0 = 32,
CV_R68_FP1 = 33,
CV_R68_FP2 = 34,
CV_R68_FP3 = 35,
CV_R68_FP4 = 36,
CV_R68_FP5 = 37,
CV_R68_FP6 = 38,
CV_R68_FP7 = 39,
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -