srlc16e_bb_config.m

基于matlab的Wimax数字中频DUC的仿真

function srlc16e_bb_config(this_block)

  % Revision History:
  %
  %   08-Jan-2007  (11:04 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     C:\Data\Projects\RF_Shelf\WiMAX_CPE\downlink\sysgen\srlc16e_bb.vhd
  %
  %

  this_block.setTopLevelLanguage('VHDL');

  this_block.setEntityName('srlc16e_bb');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('d');
  this_block.addSimulinkInport('a');
  this_block.addSimulinkInport('ce');

  this_block.addSimulinkOutport('q');
  this_block.addSimulinkOutport('q15');


  % -----------------------------
  if (this_block.inputTypesKnown)
    % do input type checking, dynamic output type and generic setup in this code block.

    % (!) Port 'd' appeared to have dynamic type in the HDL -- please add type checking as appropriate;

    if (this_block.port('a').width ~= 4);
      this_block.setError('Input data type for port "a" must have width=4.');
    end

    if (this_block.port('ce').width ~= 1);
      this_block.setError('Input data type for port "ce" must have width=1.');
    end

    this_block.port('ce').useHDLVector(false);

  % (!) Port 'q' appeared to have dynamic type in the HDL
  % --- you must add an appropriate type setting for this port
  % Start of lines added by Nabeel
  q_port = this_block.port('q');
  q_port.setType(this_block.port('d').type); 
  %  End of lines added by Nabeel
  
  % (!) Port 'q15' appeared to have dynamic type in the HDL
  % --- you must add an appropriate type setting for this port
  % Start of lines added by Nabeel
  q15_port = this_block.port('q15');
  q15_port.setType(this_block.port('d').type); 
  %  End of lines added by Nabeel
  
  end  % if(inputTypesKnown)
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     setup_as_single_rate(this_block,'sys_clk','sys_ce')
   end  % if(inputRatesKnown)
  % -----------------------------

  % (!) Custimize the following generic settings as appropriate. If any settings depend
  %      on input types, make the settings in the "inputTypesKnown" code block.
  % this_block.addGeneric('width','integer','16');
  % Start of lines added by Nabeel
  if (this_block.inputTypesKnown)
      this_block.addGeneric('width', this_block.port('d').width);
  end
  %  End of lines added by Nabeel
  

  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('srlc16e_bb.vhd');

return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.setError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.setError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------