srlc16e_bb.vhd

基于matlab的Wimax数字中频DUC的仿真

-------------------------------------------------------------------------------
-- Title      : SRLC16E Black Box
-- Project    : Sandia WiMAX DFE
-------------------------------------------------------------------------------
-- File       : srlc16e_bb.vhd
-- Author     : Ed Hemphill
-- Company    : Xilinx
-- Last update: 2007/01/08
-- Platform   : Xilinx ISE, Windows XP
-------------------------------------------------------------------------------
-- Description: This is an SRLC16E of generic width to be used as a black box
-- in System Generator.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2006/12/20  1.0      ehemphill       Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-- synopsys translate_off
library unisim;
use unisim.all;
-- synopsys translate_on

entity srlc16e_bb is

  generic (
    width : integer := 16
    );

  port (
    d       : in  std_logic_vector(width-1 downto 0);
    a       : in  std_logic_vector(3 downto 0);
    sys_clk : in  std_logic;
    sys_ce  : in  std_logic;            -- CE for System Generator
    ce      : in  std_logic;
    q       : out std_logic_vector(width-1 downto 0);
    q15     : out std_logic_vector(width-1 downto 0)
    );

end srlc16e_bb;

architecture structural of srlc16e_bb is

  component SRLC16E
    port (
      Q   : out std_ulogic;
      Q15 : out std_ulogic;
      A0  : in  std_ulogic;
      A1  : in  std_ulogic;
      A2  : in  std_ulogic;
      A3  : in  std_ulogic;
      CE  : in  std_ulogic;
      CLK : in  std_ulogic;
      D   : in  std_ulogic
      );
  end component;

  attribute syn_black_box            : boolean;
  attribute syn_black_box of SRLC16E : component is true;

begin

  L0 : for i in 0 to width-1 generate
  begin
    U0 : SRLC16E
      port map (
        Q   => q(i),
        Q15 => q15(i),
        A0  => a(0),
        A1  => a(1),
        A2  => a(2),
        A3  => a(3),
        CE  => ce,
        CLK => sys_clk,
        D   => d(i)
        );
  end generate L0;

end structural;