📄 bulkext.lst
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C51 COMPILER V7.02a BULKEXT 06/02/2004 00:34:27 PAGE 1
C51 COMPILER V7.02a, COMPILATION OF MODULE BULKEXT
OBJECT MODULE PLACED IN bulkext.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE bulkext.c BROWSE DEBUG OBJECTEXTEND
stmt level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: bulkext.c
4 // Contents: Hooks required to implement USB peripheral function.
5 //
6 // performs loopback on EP2OUT->EP6IN and EP4OUT->EP8IN
7 // this code uses the external auto pointers to first move the data
8 // to external RAM (0x2800) before looping back to the IN endpoint.
9 //
10 // Copyright (c) 2000 Cypress Semiconductor All rights reserved
11 //-----------------------------------------------------------------------------
12 #include "fx2.h"
13 #include "fx2regs.h"
14 #include "fx2sdly.h" // SYNCDELAY macro
15
16 #define LED_ADDR 0x21
17
18 extern BOOL GotSUD; // Received setup data flag
19 extern BOOL Sleep;
20 extern BOOL Rwuen;
21 extern BOOL Selfpwr;
22
23 BYTE Configuration; // Current configuration
24 BYTE AlternateSetting; // Alternate settings
25
26
27 extern BYTE num;
28
29 //-----------------------------------------------------------------------------
30 // Task Dispatcher hooks
31 // The following hooks are called by the task dispatcher.
32 //-----------------------------------------------------------------------------
33
34 void TD_Init(void) // Called once at startup
35 {
36 1 // set the CPU clock to 48MHz
37 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
38 1
39 1 // set the slave FIFO interface to 48MHz
40 1 IFCONFIG |= 0x40;
41 1
42 1 // Registers which require a synchronization delay, see section 15.14
43 1 // FIFORESET FIFOPINPOLAR
44 1 // INPKTEND OUTPKTEND
45 1 // EPxBCH:L REVCTL
46 1 // GPIFTCB3 GPIFTCB2
47 1 // GPIFTCB1 GPIFTCB0
48 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
49 1 // EPxFIFOCFG EPxGPIFFLGSEL
50 1 // PINFLAGSxx EPxFIFOIRQ
51 1 // EPxFIFOIE GPIFIRQ
52 1 // GPIFIE GPIFADRH:L
53 1 // UDMACRCH:L EPxGPIFTRIG
54 1 // GPIFTRIG
55 1
C51 COMPILER V7.02a BULKEXT 06/02/2004 00:34:27 PAGE 2
56 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
57 1 // ...these have been replaced by GPIFTC[B3:B0] registers
58 1
59 1 // default: all endpoints have their VALID bit set
60 1 // default: TYPE1 = 1 and TYPE0 = 0 --> BULK
61 1 // default: EP2 and EP4 DIR bits are 0 (OUT direction)
62 1 // default: EP6 and EP8 DIR bits are 1 (IN direction)
63 1 // default: EP2, EP4, EP6, and EP8 are double buffered
64 1
65 1 // we are just using the default values, yes this is not necessary...
66 1 EP1OUTCFG = 0xA0;
67 1 EP1INCFG = 0xA0;
68 1 SYNCDELAY; // see TRM section 15.14
69 1 EP2CFG = 0xA2;
70 1 SYNCDELAY;
71 1 EP4CFG = 0xA0;
72 1 SYNCDELAY;
73 1 EP6CFG = 0xE2;
74 1 SYNCDELAY;
75 1 EP8CFG = 0xE0;
76 1
77 1 // out endpoints do not come up armed
78 1
79 1 // since the defaults are double buffered we must write dummy byte counts twice
80 1 SYNCDELAY;
81 1 EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
82 1 SYNCDELAY;
83 1 EP2BCL = 0x80;
84 1 SYNCDELAY;
85 1 EP4BCL = 0x80; // arm EP4OUT by writing byte count w/skip.
86 1 SYNCDELAY;
87 1 EP4BCL = 0x80;
88 1
89 1 // enable dual autopointer feature
90 1 AUTOPTRSETUP |= 0x01;
91 1
92 1 Rwuen = TRUE; // Enable remote-wakeup
93 1 EZUSB_InitI2C(); // Initialize EZ-USB I2C controller
94 1 //EZUSB_WriteI2C(0x21, 0x01, &(Digit[9]));
95 1 //EZUSB_WaitForEEPROMWrite(0x21);
96 1
97 1 }
98
99
100 void TD_InitSlaveFIFO(void)
101 {
102 1 // set the CPU clock to 48MHz
103 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
104 1
105 1 EP1OUTCFG = 0xA0;
106 1 EP1INCFG = 0xA0;
107 1 SYNCDELAY;
108 1
109 1 //first,do common config for all endpoint and FIFOS
110 1
111 1 //CAUTION:if REVCTL is set to 0x03 as "Cypress highly recommends",
112 1 //the board pending all the request from controle panel.
113 1 //Ye Guodong 2004.4.28
114 1 REVCTL = 0x00;//must set REVCTL.0 and .1 to 1
115 1 SYNCDELAY;
116 1 FIFORESET = 0x80;//reset all fifos
117 1 SYNCDELAY;
C51 COMPILER V7.02a BULKEXT 06/02/2004 00:34:27 PAGE 3
118 1 FIFORESET = 0x02;
119 1 SYNCDELAY;
120 1 FIFORESET = 0x04;
121 1 SYNCDELAY;
122 1 FIFORESET = 0x06;
123 1 SYNCDELAY;
124 1 FIFORESET = 0x08;
125 1 SYNCDELAY;
126 1 FIFORESET = 0x00;
127 1 SYNCDELAY;
128 1 IFCONFIG |= 0x43;//use IFCLK pin driven by external logic
129 1 SYNCDELAY; //use slave fifo interface pin driven sync by external master
130 1 PINFLAGSAB = 0x00;//define: FLAGA as prog-level flag,FLAGB as full flag,
131 1 SYNCDELAY; //FLAGC as empty flag,no use FLAGD
132 1 PINFLAGSCD = 0x00;
133 1 PORTACFG = 0x00;//use PA7 as port pin ,not FIFO flag
134 1 FIFOPINPOLAR = 0x00;//set all slave FIFO interface pins as active low
135 1 SYNCDELAY;
136 1
137 1 //then config EP8 as follow:
138 1 EP8FIFOCFG = 0x0D;//this lets FX2 auto cnmmit IN packet, gives the ability to
139 1 //to send zero lenth packets, ande sets the slave FIFO data
140 1 // interface to 16-bits
141 1 EP8CFG = 0xE0;//set EP8 valid for IN's ,512 byte packets and 2x bufferred
142 1 EP8AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
143 1 SYNCDELAY;
144 1 EP8AUTOINLENL = 0x00;
145 1 SYNCDELAY;
146 1 EP8FIFOPFH = 0x82;
147 1 SYNCDELAY;
148 1 EP8FIFOPFL = 0x00;
149 1
150 1 // config EP6 same as endpoint8:
151 1 EP6FIFOCFG = 0x0D;//this lets FX2 auto cnmmit IN packet, gives the ability to
152 1 //to send zero lenth packets, ande sets the slave FIFO data
153 1 // interface to 16-bits
154 1 EP6CFG = 0xE2;//set EP6 valid for IN's ,512 byte packets and 2x bufferred
155 1 SYNCDELAY;
156 1 EP6AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
157 1 SYNCDELAY;
158 1 EP6AUTOINLENL = 0x00;
159 1 SYNCDELAY;
160 1 EP6FIFOPFH = 0x82;
161 1 SYNCDELAY;
162 1 EP6FIFOPFL = 0x00;
163 1
164 1 // config EP4 as follow:
165 1 EP4FIFOCFG = 0x15;//this lets FX2 auto cnmmit OUT packet, gives the ability to
166 1 //to send zero lenth packets, ande sets the slave FIFO data
167 1 // interface to 16-bits
168 1 EP4CFG = 0xA0;//set EP4 valid for OUT's ,512 byte packets and 2x bufferred
169 1 EP4AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
170 1 SYNCDELAY;
171 1 EP4AUTOINLENH = 0x00;
172 1 SYNCDELAY;
173 1 EP4FIFOPFH = 0x82;
174 1 SYNCDELAY;
175 1 EP4FIFOPFL = 0x00;
176 1
177 1 // config EP2 the same as endpoint4:
178 1 EP2FIFOCFG = 0x15;//this lets FX2 auto cnmmit OUT packet, gives the ability to
179 1 //to send zero lenth packets, ande sets the slave FIFO data
C51 COMPILER V7.02a BULKEXT 06/02/2004 00:34:27 PAGE 4
180 1 // interface to 16-bits
181 1 SYNCDELAY;
182 1 EP2CFG = 0xA2;//set EP2 valid for OUT's ,512 byte packets and 2x bufferred
183 1 EP2AUTOINLENH = 0x02;//commit a packet 0x200 in lenth every time
184 1 SYNCDELAY;
185 1 EP2AUTOINLENH = 0x00;
186 1 SYNCDELAY;
187 1 EP2FIFOPFH = 0x82;
188 1 SYNCDELAY;
189 1 EP2FIFOPFL = 0x00;
190 1
191 1 //finally,,manually arm the two OUT endpoint
192 1 SYNCDELAY;
193 1 //EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
194 1 SYNCDELAY;
195 1 //EP2BCL = 0x80;
196 1 SYNCDELAY;
197 1 //EP4BCL = 0x80; // arm EP4OUT by writing byte count w/skip.
198 1 SYNCDELAY;
199 1 //EP4BCL = 0x80;
200 1
201 1 // enable dual autopointer feature
202 1 AUTOPTRSETUP |= 0x01;
203 1
204 1 Rwuen = TRUE; // Enable remote-wakeup
205 1 EZUSB_InitI2C(); // Initialize EZ-USB I2C controller
206 1
207 1
208 1 }
209
210 void TD_Poll(void) // Called repeatedly while the device is idle
211 {
212 1 WORD i;
213 1 WORD count;
214 1 // EZUSB_WriteI2C(0x21, 0x01, &(Digit[num]));
215 1 // EZUSB_WaitForEEPROMWrite(0x21);
216 1
217 1
218 1 if(!(EP2468STAT & bmEP2EMPTY))
219 1 { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
220 2 if(!(EP2468STAT & bmEP6FULL))
221 2 { // check EP6 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
222 3 // Source is EP2OUT
223 3 APTR1H = MSB( &EP2FIFOBUF );
224 3 APTR1L = LSB( &EP2FIFOBUF );
225 3
226 3 // Destination is external RAM (at 0x2800)
227 3 AUTOPTRH2 = 0x28;
228 3 AUTOPTRL2 = 0x00;
229 3
230 3
231 3
232 3
233 3 count = (EP2BCH << 8) + EP2BCL;
234 3
235 3 for( i = 0x0000; i < count; i++ )
236 3 {
237 4 EXTAUTODAT2 = EXTAUTODAT1;
238 4 }
239 3
240 3 // Source is external RAM
241 3 APTR1H = 0x28;
C51 COMPILER V7.02a BULKEXT 06/02/2004 00:34:27 PAGE 5
242 3 APTR1L = 0x00;
243 3
244 3 // Destination is EP6IN
245 3 AUTOPTRH2 = MSB( &EP6FIFOBUF );
246 3 AUTOPTRL2 = LSB( &EP6FIFOBUF );
247 3
248 3 count = (EP2BCH << 8) + EP2BCL;
249 3
250 3 for( i = 0x0000; i < count; i++ )
251 3 {
252 4 EXTAUTODAT2 = EXTAUTODAT1;
253 4 }
254 3
255 3 EP6BCH = EP2BCH;
256 3 SYNCDELAY;
257 3 EP6BCL = EP2BCL; // arm EP6IN
258 3 SYNCDELAY;
259 3 EP2BCL = 0x80; // re(arm) EP2OUT
260 3 }
261 2 }
262 1
263 1 if(!(EP2468STAT & bmEP4EMPTY))
264 1 { // check EP4 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
265 2 if(!(EP2468STAT & bmEP8FULL))
266 2 { // check EP8 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
267 3 // setup AUTOPOINTER(s) in SFR space
268 3 // source is EP4OUT
269 3 APTR1H = MSB( &EP4FIFOBUF );
270 3 APTR1L = LSB( &EP4FIFOBUF );
271 3
272 3 // Destination is external RAM (at 0x2A00)
273 3 AUTOPTRH2 = 0x2A;
274 3 AUTOPTRL2 = 0x00;
275 3
276 3 count = (EP4BCH << 8) + EP4BCL;
277 3
278 3 for( i = 0x0000; i < count; i++ )
279 3 {
280 4 EXTAUTODAT2 = EXTAUTODAT1;
281 4 }
282 3
283 3 // Source is external RAM
284 3 APTR1H = 0x2A;
285 3 APTR1L = 0x00;
286 3
287 3 // Destination is EP8IN
288 3 AUTOPTRH2 = MSB( &EP8FIFOBUF );;
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