i386-opc.h

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{"fdiv", 2, 0xd8f0, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdiv", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdiv", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdiv", 0, 0xdcf1, _, NoModrm, 0, 0, 0},
{"fdivp", 1, 0xdaf0, _, ShortForm, FloatReg, 0, 0},
{"fdivp", 2, 0xdaf0, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdivp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdivp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdivp", 0, 0xdef1, _, NoModrm, 0, 0, 0},
{"fdivs", 1, 0xd8, 6, Modrm, Mem, 0, 0},
{"fidivl", 1, 0xda, 6, Modrm, Mem, 0, 0},
{"fdivl", 1, 0xdc, 6, Modrm, Mem, 0, 0},
{"fidivs", 1, 0xde, 6, Modrm, Mem, 0, 0},

/* div reverse */
{"fdivr", 1, 0xd8f8, _, ShortForm, FloatReg, 0, 0},
{"fdivr", 2, 0xd8f8, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdivr", 2, 0xdcf0, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdivr", 2, 0xdcf8, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdivr", 0, 0xdcf9, _, NoModrm, 0, 0, 0},
{"fdivrp", 1, 0xdaf8, _, ShortForm, FloatReg, 0, 0},
{"fdivrp", 2, 0xdaf8, _, ShortForm, FloatReg, FloatAcc, 0},
#ifdef NON_BROKEN_OPCODES
{"fdivrp", 2, 0xdef0, _, ShortForm, FloatAcc, FloatReg, 0},
#else
{"fdivrp", 2, 0xdef8, _, ShortForm, FloatAcc, FloatReg, 0},
#endif
{"fdivrp", 0, 0xdef9, _, NoModrm, 0, 0, 0},
{"fdivrs", 1, 0xd8, 7, Modrm, Mem, 0, 0},
{"fidivrl", 1, 0xda, 7, Modrm, Mem, 0, 0},
{"fdivrl", 1, 0xdc, 7, Modrm, Mem, 0, 0},
{"fidivrs", 1, 0xde, 7, Modrm, Mem, 0, 0},

{"f2xm1", 0,   0xd9f0, _, NoModrm, 0, 0, 0},
{"fyl2x", 0,   0xd9f1, _, NoModrm, 0, 0, 0},
{"fptan", 0,   0xd9f2, _, NoModrm, 0, 0, 0},
{"fpatan", 0,  0xd9f3, _, NoModrm, 0, 0, 0},
{"fxtract", 0, 0xd9f4, _, NoModrm, 0, 0, 0},
{"fprem1", 0,  0xd9f5, _, NoModrm, 0, 0, 0},
{"fdecstp", 0,  0xd9f6, _, NoModrm, 0, 0, 0},
{"fincstp", 0,  0xd9f7, _, NoModrm, 0, 0, 0},
{"fprem", 0,   0xd9f8, _, NoModrm, 0, 0, 0},
{"fyl2xp1", 0, 0xd9f9, _, NoModrm, 0, 0, 0},
{"fsqrt", 0,   0xd9fa, _, NoModrm, 0, 0, 0},
{"fsincos", 0, 0xd9fb, _, NoModrm, 0, 0, 0},
{"frndint", 0, 0xd9fc, _, NoModrm, 0, 0, 0},
{"fscale", 0,  0xd9fd, _, NoModrm, 0, 0, 0},
{"fsin", 0,    0xd9fe, _, NoModrm, 0, 0, 0},
{"fcos", 0,    0xd9ff, _, NoModrm, 0, 0, 0},

{"fchs", 0, 0xd9e0, _, NoModrm, 0, 0, 0},
{"fabs", 0, 0xd9e1, _, NoModrm, 0, 0, 0},

/* processor control */
{"fninit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
{"finit", 0, 0xdbe3, _, NoModrm, 0, 0, 0},
{"fldcw", 1, 0xd9, 5, Modrm, Mem, 0, 0},
{"fnstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
{"fstcw", 1, 0xd9, 7, Modrm, Mem, 0, 0},
{"fnstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
{"fnstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
{"fnstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
{"fstsw", 1, 0xdfe0, _, NoModrm, Acc, 0, 0},
{"fstsw", 1, 0xdd, 7, Modrm, Mem, 0, 0},
{"fstsw", 0, 0xdfe0, _, NoModrm, 0, 0, 0},
{"fnclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
{"fclex", 0, 0xdbe2, _, NoModrm, 0, 0, 0},
/*
 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
 instructions;  i'm not sure how to add them or how they are different.
 My 386/387 book offers no details about this.
*/
{"fnstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
{"fstenv", 1, 0xd9, 6, Modrm, Mem, 0, 0},
{"fldenv", 1, 0xd9, 4, Modrm, Mem, 0, 0},
{"fnsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
{"fsave", 1, 0xdd, 6, Modrm, Mem, 0, 0},
{"frstor", 1, 0xdd, 4, Modrm, Mem, 0, 0},

{"ffree", 1, 0xddc0, _, ShortForm, FloatReg, 0, 0},
{"fnop", 0, 0xd9d0, _, NoModrm, 0, 0, 0},
{"fwait", 0, 0x9b, _, NoModrm, 0, 0, 0},

/*
mmx support
*/
{"emms", 0,0x0f77, _, NoModrm, 0,	0,		 0},
{"movd", 2,0x0f6e, _, Modrm, Reg32|Mem, MmxReg,0},
{"movd", 2,0x0f7e, _, Modrm, MmxReg,Reg32|Mem, 0},
{"movq", 2,0x0f6f, _, Modrm,MmxReg|Mem, MmxReg,		0},
{"movq", 2,0x0f7f, _, Modrm, MmxReg,Mem|MmxReg,		0},
{"packsswb",2,0x0f63,_,Modrm,Mem|MmxReg,	MmxReg,		0},
{"packssdw",2,0x0f6b,_,Modrm,Mem|MmxReg,	MmxReg,		0},
{"packuswb",2,0x0f67,_,Modrm,Mem|MmxReg,	MmxReg,		0},
{"paddb",2,0x0ffc, _, Modrm, Mem|MmxReg,   MmxReg,		0},
{"paddw",2,0x0ffd, _, Modrm, Mem|MmxReg,   MmxReg,		0},
{"paddd",2,0x0ffe, _, Modrm, Mem|MmxReg,	MmxReg,		0},
{"paddsb",2,0x0fec,_, Modrm, Mem|MmxReg,	MmxReg,		0},
{"paddsw",2,0x0fed,_, Modrm, Mem|MmxReg,	MmxReg,		0},
{"paddusb",2,0x0fdc,_,Modrm, Mem|MmxReg,   MmxReg,		0},
{"paddusw",2,0x0fdd,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pand",2, 0x0fdb, _, Modrm, Mem|MmxReg,	MmxReg,		0},
{"pandn",2,0x0fdf, _, Modrm, Mem|MmxReg,	MmxReg,		0},
{"pcmpeqb",2,0x0f74,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pcmpeqw",2,0x0f75,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pcmpeqd",2,0x0f76,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pcmpgtb",2,0x0f64,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pcmpgtw",2,0x0f65,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pcmpgtd",2,0x0f66,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pmaddwd",2,0x0ff5,_,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pmulhw",2,0x0fe5, _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pmullw",2,0x0fd5, _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"por",2,0x0feb,    _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psllw",2,0x0ff1,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psllw",2,0x0f71,  6,Modrm, Imm8,			MmxReg,		0},
{"pslld",2,0x0ff2,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pslld",2,0x0f72,  6,Modrm, Imm8,	MmxReg,		0},
{"psllq",2,0x0ff3,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psllq",2,0x0f73,  6,Modrm, Imm8,			MmxReg,		0},
{"psraw",2,0x0fe1,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psraw",2,0x0f71,  4,Modrm, Imm8,			MmxReg,		0},
{"psrad",2,0x0fe2,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psrad",2,0x0f72,  4,Modrm, Imm8,			MmxReg,		0},
{"psrlw",2,0x0fd1,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psrlw",2,0x0f71,  2,Modrm, Imm8,			MmxReg,		0},
{"psrld",2,0x0fd2,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psrld",2,0x0f72,  2,Modrm, Imm8,			MmxReg,		0},
{"psrlq",2,0x0fd3,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psrlq",2,0x0f73,  2,Modrm, Imm8,			MmxReg,		0},
{"psubb",2,0x0ff8,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psubw",2,0x0ff9,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psubd",2,0x0ffa,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psubsb",2,0x0fe8,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psubsw",2,0x0fe9,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psubusb",2,0x0fd8,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"psubusw",2,0x0fd9,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"punpckhbw",2,0x0f68,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"punpckhwd",2,0x0f69,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"punpckhdq",2,0x0f6a,  _,Modrm, Mem|MmxReg,	MmxReg,		0},

{"punpcklbw",2,0x0f60,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"punpcklwd",2,0x0f61,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"punpckldq",2,0x0f62,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"punpckldq",2,0x0f62,  _,Modrm, Mem|MmxReg,	MmxReg,		0},
{"pxor",	2,0x0fef,	_,Modrm, Mem|MmxReg,	MmxReg,		0},


/*
  opcode prefixes; we allow them as seperate insns too
  (see prefix table below)
*/
{"aword", 0, 0x67, _, NoModrm, 0, 0, 0},
{"word", 0, 0x66, _, NoModrm, 0, 0, 0},
{"lock", 0, 0xf0, _, NoModrm, 0, 0, 0},
{"cs", 0, 0x2e, _, NoModrm, 0, 0, 0},
{"ds", 0, 0x3e, _, NoModrm, 0, 0, 0},
{"es", 0, 0x26, _, NoModrm, 0, 0, 0},
{"fs", 0, 0x64, _, NoModrm, 0, 0, 0},
{"gs", 0, 0x65, _, NoModrm, 0, 0, 0},
{"ss", 0, 0x36, _, NoModrm, 0, 0, 0},
{"rep", 0, 0xf3, _, NoModrm, 0, 0, 0},
{"repe", 0, 0xf3, _, NoModrm, 0, 0, 0},
{ "repne", 0, 0xf2, _, NoModrm, 0, 0, 0},

{"cpuid",0,0x0fa2,_,NoModrm,0,0,0},
{"bswap",1,0x0fc8,_,ShortForm,Reg32,0,0},
{"invd",0,0x0f08,_,NoModrm,0,0,0},
{"rdtsc",0,0x0f31,_,NoModrm,0,0,0},

{"", 0, 0, 0, 0, 0, 0, 0}	/* sentinel */
};
#undef _

static template *i386_optab_end 
  = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);

/* 386 register table */

reg_entry i386_regtab[] = {
  /* 32 bit regs */
  {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
  {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
  /* 8 bit regs */
  {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
  {"bl", Reg8, 3},
  {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
  /* 16 bit regs */
  {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
  {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
  /* segment registers */
  {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
  {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
  /* control registers */
  {"cr0", Control, 0},   {"cr2", Control, 2},   {"cr3", Control, 3},
  /* debug registers */
  {"db0", Debug, 0},   {"db1", Debug, 1},   {"db2", Debug, 2},
  {"db3", Debug, 3},   {"db6", Debug, 6},   {"db7", Debug, 7},
  /* test registers */
  {"tr6", Test, 6}, {"tr7", Test, 7},
  /* float registers */
  {"st(0)", FloatReg|FloatAcc, 0},
  {"st", FloatReg|FloatAcc, 0},
  {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 
  {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 
  {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7},
  /* mmx registers */
  {"mm0", MmxReg,0},
  {"mm1", MmxReg,1},
  {"mm2", MmxReg,2},
  {"mm3", MmxReg,3},
  {"mm4", MmxReg,4},
  {"mm5", MmxReg,5},
  {"mm6", MmxReg,6},
  {"mm7", MmxReg,7}
};

#define MAX_REG_NAME_SIZE 8	/* for parsing register names from input */
#define MAX_REG_NAMES	(sizeof(i386_regtab)/sizeof(reg_entry))
static reg_entry *i386_regtab_end
  = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);

/* segment stuff */
static seg_entry cs = { "cs", 0x2e };
static seg_entry ds = { "ds", 0x3e };
static seg_entry ss = { "ss", 0x36 };
static seg_entry es = { "es", 0x26 };
static seg_entry fs = { "fs", 0x64 };
static seg_entry gs = { "gs", 0x65 };
static seg_entry null = { "", 0x0 };

/*
  This table is used to store the default segment register implied by all
  possible memory addressing modes.
  It is indexed by the mode & modrm entries of the modrm byte as follows:
      index = (mode<<3) | modrm;
*/
static seg_entry *one_byte_segment_defaults[] = {
  /* mode 0 */
  &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
  /* mode 1 */
  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
  /* mode 2 */
  &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
  /* mode 3 --- not a memory reference; never referenced */
};

static seg_entry *two_byte_segment_defaults[] = {
  /* mode 0 */
  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
  /* mode 1 */
  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
  /* mode 2 */
  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
  /* mode 3 --- not a memory reference; never referenced */
};

static prefix_entry i386_prefixtab[] = {
  { "addr16", 0x67 },		/* address size prefix ==> 16bit addressing
				 * (How is this useful?) */
#define WORD_PREFIX_OPCODE 0x66
  { "data16", 0x66 },		/* operand size prefix */
  { "lock", 0xf0 },		/* bus lock prefix */
  { "wait", 0x9b },		/* wait for coprocessor */
  { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
  { "es", 0x26 }, { "fs", 0x64 },
  { "gs", 0x65 }, { "ss", 0x36 },
/* REPE & REPNE used to detect rep/repne with a non-string instruction */
#define REPNE 0xf2
#define REPE  0xf3
  { "rep", 0xf3 }, { "repe", 0xf3 }, /* repeat string instructions */
  { "repne", 0xf2 }
};

static prefix_entry *i386_prefixtab_end
  = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);