i386-opc.h

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/* i386-opcode.h -- Intel 80386 opcode table */
   
static template i386_optab[] = {

#define _ None
/* move instructions */
{ "mov", 2, 0xa0, _, DW|NoModrm, Disp32, Acc, 0 },
{ "mov", 2, 0x88, _, DW|Modrm, Reg, Reg|Mem, 0 },
{ "mov", 2, 0xb0, _, ShortFormW, Imm, Reg, 0 },
{ "mov", 2, 0xc6, _,  W|Modrm,  Imm, Reg|Mem, 0 },
{ "mov", 2, 0x8c, _, D|Modrm,  SReg3|SReg2, Reg16|Mem16, 0 },
/* move to/from control debug registers */
{ "mov", 2, 0x0f20, _, D|Modrm, Control, Reg32, 0},
{ "mov", 2, 0x0f21, _, D|Modrm, Debug, Reg32, 0},
{ "mov", 2, 0x0f24, _, D|Modrm, Test, Reg32, 0},

/* move with sign extend */
/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
   conflict with the "movs" string move instruction.  Thus,
   {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem,  Reg16|Reg32, 0},
   is not kosher; we must seperate the two instructions. */
{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem,  Reg32, 0},
{"movsbw", 2, 0x660fbe, _, ReverseRegRegmem|Modrm, Reg8|Mem,  Reg16, 0},
{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},

/* move with zero extend */
{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, Reg8|Mem, Reg16|Reg32, 0},
{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, Reg16|Mem, Reg32, 0},

/* push instructions */
{"push", 1, 0x50, _, ShortForm, WordReg,0,0 },
{"push", 1, 0xff, 0x6,  Modrm, WordReg|WordMem, 0, 0 },
{"push", 1, 0x6a, _, NoModrm, Imm8S, 0, 0},
{"push", 1, 0x68, _, NoModrm, Imm32, 0, 0},
{"push", 1, 0x06, _,  Seg2ShortForm, SReg2,0,0 },
{"push", 1, 0x0fa0, _, Seg3ShortForm, SReg3,0,0 },
/* push all */
{"pusha", 0, 0x60, _, NoModrm, 0, 0, 0 },

/* pop instructions */
{"pop", 1, 0x58, _, ShortForm, WordReg,0,0 },
{"pop", 1, 0x8f, 0x0,  Modrm, WordReg|WordMem, 0, 0 },
#define POP_SEG_SHORT 0x7
{"pop", 1, 0x07, _,  Seg2ShortForm, SReg2,0,0 },
{"pop", 1, 0x0fa1, _, Seg3ShortForm, SReg3,0,0 },
/* pop all */
{"popa", 0, 0x61, _, NoModrm, 0, 0, 0 },

/* xchg exchange instructions
   xchg commutes:  we allow both operand orders */
{"xchg", 2, 0x90, _, ShortForm, WordReg, Acc, 0 },
{"xchg", 2, 0x90, _, ShortForm, Acc, WordReg, 0 },
{"xchg", 2, 0x86, _, W|Modrm, Reg, Reg|Mem, 0 },
{"xchg", 2, 0x86, _, W|Modrm, Reg|Mem, Reg, 0 },
/* xadd: exchange and add */
{"xadd", 2, 0x0fc0,_, DW|Modrm, Reg, Mem|Reg, 0 },

/* in/out from ports */
{"in", 2, 0xe4, _, W|NoModrm, Imm8, Acc, 0 },
{"in", 2, 0xec, _, W|NoModrm, InOutPortReg, Acc, 0 },
{"out", 2, 0xe6, _, W|NoModrm, Acc, Imm8, 0 },
{"out", 2, 0xee, _, W|NoModrm, Acc, InOutPortReg, 0 },

/* load effective address */
{"lea", 2, 0x8d, _, Modrm, WordMem, WordReg, 0 },

/* load segment registers from memory */
{"lds", 2, 0xc5, _, Modrm, Mem, Reg32, 0},
{"les", 2, 0xc4, _, Modrm, Mem, Reg32, 0},
{"lfs", 2, 0x0fb4, _, Modrm, Mem, Reg32, 0},
{"lgs", 2, 0x0fb5, _, Modrm, Mem, Reg32, 0},
{"lss", 2, 0x0fb2, _, Modrm, Mem, Reg32, 0},

/* flags register instructions */
{"clc", 0, 0xf8, _, NoModrm, 0, 0, 0},
{"cld", 0, 0xfc, _, NoModrm, 0, 0, 0},
{"cli", 0, 0xfa, _, NoModrm, 0, 0, 0},
{"clts", 0, 0x0f06, _, NoModrm, 0, 0, 0},
{"cmc", 0, 0xf5, _, NoModrm, 0, 0, 0},
{"lahf", 0, 0x9f, _, NoModrm, 0, 0, 0},
{"sahf", 0, 0x9e, _, NoModrm, 0, 0, 0},
{"pushf", 0, 0x9c, _, NoModrm, 0, 0, 0},
{"popf", 0, 0x9d, _, NoModrm, 0, 0, 0},
{"stc", 0, 0xf9, _, NoModrm, 0, 0, 0},
{"std", 0, 0xfd, _, NoModrm, 0, 0, 0},
{"sti", 0, 0xfb, _, NoModrm, 0, 0, 0},

{"add", 2, 0x0,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"add", 2, 0x83, 0,  Modrm, Imm8S, WordReg|WordMem, 0},
{"add", 2, 0x4,  _,  W|NoModrm, Imm,  Acc,    0},
{"add", 2, 0x80, 0, W|Modrm, Imm, Reg|Mem, 0},

{"inc", 1, 0x40, _, ShortForm, WordReg, 0, 0},
{"inc", 1, 0xfe, 0, W|Modrm, Reg|Mem, 0, 0},

{"sub", 2, 0x28,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"sub", 2, 0x83, 5,  Modrm, Imm8S, WordReg|WordMem, 0},
{"sub", 2, 0x2c,  _,  W|NoModrm, Imm,  Acc,    0},
{"sub", 2, 0x80, 5,  W|Modrm, Imm, Reg|Mem, 0},

{"dec", 1, 0x48, _, ShortForm, WordReg, 0, 0},
{"dec", 1, 0xfe, 1, W|Modrm, Reg|Mem, 0, 0},

{"sbb", 2, 0x18,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"sbb", 2, 0x83, 3,  Modrm, Imm8S, WordReg|WordMem, 0},
{"sbb", 2, 0x1c,  _,  W|NoModrm, Imm,  Acc,    0},
{"sbb", 2, 0x80, 3,  W|Modrm, Imm, Reg|Mem, 0},

{"cmp", 2, 0x38,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"cmp", 2, 0x83, 7,  Modrm, Imm8S, WordReg|WordMem, 0},
{"cmp", 2, 0x3c,  _,  W|NoModrm, Imm,  Acc,    0},
{"cmp", 2, 0x80, 7,  W|Modrm, Imm, Reg|Mem, 0},
{"cmpxchg",2,0x0fb0,_,DW|Modrm,Reg,Reg|Mem,0 },
{"cmpxchg8b",1,0x0fc7,1,Modrm, Mem ,0,0 },

{"test", 2, 0x84, _, W|Modrm, Reg|Mem, Reg, 0},
{"test", 2, 0x84, _, W|Modrm, Reg, Reg|Mem, 0},
{"test", 2, 0xa8, _, W|NoModrm, Imm, Acc, 0},
{"test", 2, 0xf6, 0, W|Modrm, Imm, Reg|Mem, 0},

{"and", 2, 0x20,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"and", 2, 0x83, 4,  Modrm, Imm8S, WordReg|WordMem, 0},
{"and", 2, 0x24,  _,  W|NoModrm, Imm,  Acc,    0},
{"and", 2, 0x80, 4,  W|Modrm, Imm, Reg|Mem, 0},

{"or", 2, 0x08,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"or", 2, 0x83, 1,  Modrm, Imm8S, WordReg|WordMem, 0},
{"or", 2, 0x0c,  _,  W|NoModrm, Imm,  Acc,    0},
{"or", 2, 0x80, 1,  W|Modrm, Imm, Reg|Mem, 0},

{"xor", 2, 0x30,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"xor", 2, 0x83, 6,  Modrm, Imm8S, WordReg|WordMem, 0},
{"xor", 2, 0x34,  _,  W|NoModrm, Imm,  Acc,    0},
{"xor", 2, 0x80, 6,  W|Modrm, Imm, Reg|Mem, 0},

{"adc", 2, 0x10,  _, DW|Modrm, Reg, Reg|Mem, 0},
{"adc", 2, 0x83, 2,  Modrm, Imm8S, WordReg|WordMem, 0},
{"adc", 2, 0x14,  _,  W|NoModrm, Imm,  Acc,    0},
{"adc", 2, 0x80, 2,  W|Modrm, Imm, Reg|Mem, 0},

{"neg", 1, 0xf6, 3, W|Modrm, Reg|Mem, 0, 0},
{"not", 1, 0xf6, 2, W|Modrm, Reg|Mem, 0, 0},

{"aaa", 0, 0x37, _, NoModrm, 0, 0, 0},
{"aas", 0, 0x3f, _, NoModrm, 0, 0, 0},
{"daa", 0, 0x27, _, NoModrm, 0, 0, 0},
{"das", 0, 0x2f, _, NoModrm, 0, 0, 0},
{"aad", 0, 0xd50a, _, NoModrm, 0, 0, 0},
{"aam", 0, 0xd40a, _, NoModrm, 0, 0, 0},

/* conversion insns */
/* conversion:  intel naming */
{"cbw", 0, 0x6698, _, NoModrm, 0, 0, 0},
{"cwd", 0, 0x6699, _, NoModrm, 0, 0, 0},
{"cwde", 0, 0x98, _, NoModrm, 0, 0, 0},
{"cdq", 0, 0x99, _, NoModrm, 0, 0, 0},
/*  att naming */
{"cbtw", 0, 0x6698, _, NoModrm, 0, 0, 0},
{"cwtl", 0, 0x98, _, NoModrm, 0, 0, 0},
{"cwtd", 0, 0x6699, _, NoModrm, 0, 0, 0},
{"cltd", 0, 0x99, _, NoModrm, 0, 0, 0},

/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
   expanding 64-bit multiplies, and *cannot* be selected to accomplish
   'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
   These multiplies can only be selected with single opearnd forms. */
{"mul",  1, 0xf6, 4, W|Modrm, Reg|Mem, 0, 0},
{"imul", 1, 0xf6, 5, W|Modrm, Reg|Mem, 0, 0},

/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
   These instructions are exceptions:  'imul $2, %eax, %ecx' would put
   '%eax' in the reg field and '%ecx' in the regmem field if we did not
   switch them. */
{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, WordReg|Mem, WordReg, 0},
{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, Imm8S, WordReg|Mem, WordReg},
{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, Imm16|Imm32, WordReg|Mem, WordReg},
/*
  imul with 2 operands mimicks imul with 3 by puting register both
  in i.rm.reg & i.rm.regmem fields
*/
{"imul", 2, 0x6b, _, Modrm|imulKludge, Imm8S, WordReg, 0},
{"imul", 2, 0x69, _, Modrm|imulKludge, Imm16|Imm32, WordReg, 0},
{"div", 1, 0xf6, 6, W|Modrm, Reg|Mem, 0, 0},
{"div", 2, 0xf6, 6, W|Modrm, Reg|Mem, Acc, 0},
{"idiv", 1, 0xf6, 7, W|Modrm, Reg|Mem, 0, 0},
{"idiv", 2, 0xf6, 7, W|Modrm, Reg|Mem, Acc, 0},

{"rol", 2, 0xd0, 0, W|Modrm, Imm1, Reg|Mem, 0},
{"rol", 2, 0xc0, 0, W|Modrm, Imm8, Reg|Mem, 0},
{"rol", 2, 0xd2, 0, W|Modrm, ShiftCount, Reg|Mem, 0},
{"rol", 1, 0xd0, 0, W|Modrm, Reg|Mem, 0, 0},

{"ror", 2, 0xd0, 1, W|Modrm, Imm1, Reg|Mem, 0},
{"ror", 2, 0xc0, 1, W|Modrm, Imm8, Reg|Mem, 0},
{"ror", 2, 0xd2, 1, W|Modrm, ShiftCount, Reg|Mem, 0},
{"ror", 1, 0xd0, 1, W|Modrm, Reg|Mem, 0, 0},

{"rcl", 2, 0xd0, 2, W|Modrm, Imm1, Reg|Mem, 0},
{"rcl", 2, 0xc0, 2, W|Modrm, Imm8, Reg|Mem, 0},
{"rcl", 2, 0xd2, 2, W|Modrm, ShiftCount, Reg|Mem, 0},
{"rcl", 1, 0xd0, 2, W|Modrm, Reg|Mem, 0, 0},

{"rcr", 2, 0xd0, 3, W|Modrm, Imm1, Reg|Mem, 0},
{"rcr", 2, 0xc0, 3, W|Modrm, Imm8, Reg|Mem, 0},
{"rcr", 2, 0xd2, 3, W|Modrm, ShiftCount, Reg|Mem, 0},
{"rcr", 1, 0xd0, 3, W|Modrm, Reg|Mem, 0, 0},

{"sal", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
{"sal", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
{"sal", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
{"sal", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},
{"shl", 2, 0xd0, 4, W|Modrm, Imm1, Reg|Mem, 0},
{"shl", 2, 0xc0, 4, W|Modrm, Imm8, Reg|Mem, 0},
{"shl", 2, 0xd2, 4, W|Modrm, ShiftCount, Reg|Mem, 0},
{"shl", 1, 0xd0, 4, W|Modrm, Reg|Mem, 0, 0},

{"shld", 3, 0x0fa4, _, Modrm, Imm8, WordReg, WordReg|Mem},
{"shld", 3, 0x0fa5, _, Modrm, ShiftCount, WordReg, WordReg|Mem},

{"shr", 2, 0xd0, 5, W|Modrm, Imm1, Reg|Mem, 0},
{"shr", 2, 0xc0, 5, W|Modrm, Imm8, Reg|Mem, 0},
{"shr", 2, 0xd2, 5, W|Modrm, ShiftCount, Reg|Mem, 0},
{"shr", 1, 0xd0, 5, W|Modrm, Reg|Mem, 0, 0},

{"shrd", 3, 0x0fac, _, Modrm, Imm8, WordReg, WordReg|Mem},
{"shrd", 3, 0x0fad, _, Modrm, ShiftCount, WordReg, WordReg|Mem},

{"sar", 2, 0xd0, 7, W|Modrm, Imm1, Reg|Mem, 0},
{"sar", 2, 0xc0, 7, W|Modrm, Imm8, Reg|Mem, 0},
{"sar", 2, 0xd2, 7, W|Modrm, ShiftCount, Reg|Mem, 0},
{"sar", 1, 0xd0, 7, W|Modrm, Reg|Mem, 0, 0},

/* control transfer instructions */
#define CALL_PC_RELATIVE 0xe8
{"call", 1, 0xe8, _, JumpDword, Disp32, 0, 0},
{"call", 1, 0xff, 2, Modrm, Reg|Mem|JumpAbsolute, 0, 0},
#define CALL_FAR_IMMEDIATE 0x9a
{"lcall", 2, 0x9a, _, JumpInterSegment, Imm16, Abs32, 0},
{"lcall", 1, 0xff, 3, Modrm, Mem, 0, 0},

#define JUMP_PC_RELATIVE 0xeb
{"jmp", 1, 0xeb, _, Jump, Disp, 0, 0},
{"jmp", 1, 0xff, 4, Modrm, Reg32|Mem|JumpAbsolute, 0, 0},
#define JUMP_FAR_IMMEDIATE 0xea
{"ljmp", 2, 0xea, _, JumpInterSegment, Imm16, Imm32, 0},
{"ljmp", 1, 0xff, 5, Modrm, Mem, 0, 0},

{"ret", 0, 0xc3, _, NoModrm, 0, 0, 0},
{"ret", 1, 0xc2, _, NoModrm, Imm16, 0, 0},
{"lret", 0, 0xcb, _, NoModrm, 0, 0, 0},
{"lret", 1, 0xca, _, NoModrm, Imm16, 0, 0},
{"enter", 2, 0xc8, _, NoModrm, Imm16, Imm8, 0},
{"leave", 0, 0xc9, _, NoModrm, 0, 0, 0},

/* conditional jumps */
{"jo", 1, 0x70, _, Jump, Disp, 0, 0},

{"jno", 1, 0x71, _, Jump, Disp, 0, 0},

{"jb", 1, 0x72, _, Jump, Disp, 0, 0},
{"jc", 1, 0x72, _, Jump, Disp, 0, 0},
{"jnae", 1, 0x72, _, Jump, Disp, 0, 0},

{"jnb", 1, 0x73, _, Jump, Disp, 0, 0},
{"jnc", 1, 0x73, _, Jump, Disp, 0, 0},
{"jae", 1, 0x73, _, Jump, Disp, 0, 0},

{"je", 1, 0x74, _, Jump, Disp, 0, 0},
{"jz", 1, 0x74, _, Jump, Disp, 0, 0},

{"jne", 1, 0x75, _, Jump, Disp, 0, 0},
{"jnz", 1, 0x75, _, Jump, Disp, 0, 0},

{"jbe", 1, 0x76, _, Jump, Disp, 0, 0},
{"jna", 1, 0x76, _, Jump, Disp, 0, 0},

{"jnbe", 1, 0x77, _, Jump, Disp, 0, 0},
{"ja", 1, 0x77, _, Jump, Disp, 0, 0},

{"js", 1, 0x78, _, Jump, Disp, 0, 0},

{"jns", 1, 0x79, _, Jump, Disp, 0, 0},

{"jp", 1, 0x7a, _, Jump, Disp, 0, 0},
{"jpe", 1, 0x7a, _, Jump, Disp, 0, 0},

{"jnp", 1, 0x7b, _, Jump, Disp, 0, 0},