win32.md

window下的c编译器。

;;
stmt: NEI(BANDU(INDIRC(addr),con),zero) "\ttestb\t%1,%0\n\tjne\t%a\n"
stmt: EQI(BANDU(reg,con),zero) "\ttestl\t%1,%0\n\tje\t%a\n" 1
;;stmt: EQI(BANDU(reg,con16),zero) "\ttestw\t%1,%0\n\tje\t%a\n" 
stmt: NEI(BANDU(reg,con),zero) "\ttestl\t%1,%0\n\tjne\t%a\n"

;; Comparing directly a memory location to an immediate constant
;;
stmt: NEI(CVSI(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjne\t%a\n"
stmt: NEI(CVSU(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjne\t%a\n"
stmt: LEI(CVSI(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjle\t%a\n"
stmt: LEI(CVSU(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjbe\t%a\n"
stmt: LTI(CVSI(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjl\t%a\n"
stmt: LTI(CVSU(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjb\t%a\n"
stmt: GTI(CVSI(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjg\t%a\n"
stmt: GTU(CVSU(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tja\t%a\n"
stmt: GEI(CVSI(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjge\t%a\n"
stmt: GEI(CVSU(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tjae\t%a\n"
stmt: EQI(CVSI(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tje\t%a\n"
stmt: EQI(CVSU(INDIRS(addr)),con) "\tcmpw\t%1,%0\n\tje\t%a\n"

stmt: NEI(CVCI(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjne\t%a\n"
stmt: NEI(CVCU(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjne\t%a\n"
;;
;; immediate comparisons of a byte register with a constant
;; without any conversions
;;
stmt: NEI(CVCI(reg),con) "\tcmpb\t%1,%0\n\tjne\t%a\n"
stmt: NEI(CVCU(reg),con) "\tcmpb\t%1,%0\n\tjne\t%a\n"
stmt: EQI(CVCI(reg),con) "\tcmpb\t%1,%0\n\tje\t%a\n"
stmt: EQI(CVCU(reg),con) "\tcmpb\t%1,%0\n\tje\t%a\n"
stmt: EQI(CVCI(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tje\t%a\n"
stmt: EQI(CVCU(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tje\t%a\n"
stmt: LEI(CVCI(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjle\t%a\n"
stmt: LEU(CVCU(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjbe\t%a\n"
stmt: LTI(CVCI(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjl\t%a\n"
stmt: LTU(CVCU(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjb\t%a\n"
stmt: GTI(CVCI(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjg\t%a\n"
stmt: GTU(CVCU(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tja\t%a\n"
stmt: GEI(CVCI(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjge\t%a\n"
stmt: GEU(CVCU(INDIRC(addr)),con) "\tcmpb\t%1,%0\n\tjae\t%a\n"

base: ADDP(ADDRGP,acon) "%a+%1"
;;
;; This happens in the C idiom:
;; if (!somfn())
;; when somfn returns an unsigned short.
;;
stmt: NEI(CVSU(CVUS(reg)),zero)   "\torw\t%0,%0\n\tjne\t%a\n"
stmt: EQI(CVSU(CVUS(reg)),zero)   "\torw\t%0,%0\n\tje\t%a\n"
stmt: NEI(CVSI(CVIS(reg)),zero)   "\torw\t%0,%0\n\tjne\t%a\n"
stmt: EQI(CVSI(CVIS(reg)),zero)   "\torw\t%0,%0\n\tjne\t%a\n"

;; Some floating point constnts can be generated directly by the
;; machine. This is not faster but should save space in the data
;; segment once I convice the front end not to generate them.

dcon1: CNSTD "\tfld1\n" dequal(a,1)
dcon1: CNSTL "\tfld1\n" dequal(a,1)
dcon0: CNSTD "\tfldz\n" dequal(a,0)
dcon0: CNSTL "\tfldz\n" dequal(a,0)
dcon1: CNSTF "\tfld1\n" fequal(a,1)
dcon0: CNSTF "\tfldz\n" fequal(a,0)
freg: dcon1 "%0"
freg: dcon0 "%0"

;; This floating point operations were missing from the machine
;; description.

freg: DIVD(freg,CVID(INDIRI(addr))) "\tfidivl\t%1\n"
freg: DIVD(CVID(INDIRI(addr)),freg) "\tfidivrl\t%0\n"
freg: DIVD(freg,CVID(CVSI(INDIRS(addr)))) "\tfidivs\t%1\n"
freg: DIVD(CVID(CVSI(INDIRS(addr))),freg) "\tfidivrs\t%0\n"
freg: MULD(freg,CVID(INDIRI(addr))) "\tfimull\t%1\n"
freg: MULD(CVID(INDIRI(addr)),freg) "\tfimull\t%0\n"
freg: MULD(freg,CVID(CVSI(INDIRS(addr)))) "\tfimuls\t%1\n"
freg: SUBD(freg,CVID(INDIRI(addr))) "\tfisubl\t%1\n"
freg: SUBD(CVID(INDIRI(addr)),freg) "\tfisubrl\t%0\n"
freg: SUBD(freg,CVID(CVSI(INDIRS(addr)))) "\tfisubs\t%1\n"
freg: SUBD(CVID(CVSI(INDIRS(addr))),freg) "\tfisubrs\t%0\n"
freg: ADDD(freg,CVID(INDIRI(addr))) "\tfiaddl\t%1\n"
freg: ADDD(CVID(INDIRI(addr)),freg) "\tfiaddl\t%0\n"
freg: ADDD(freg,CVID(CVSI(INDIRS(addr)))) "\tfiadds\t%1\n"
freg: ADDD(freg,CVFD(INDIRF(addr))) "\tfdivs\t%1\n"
freg: SUBD(freg,CVFD(INDIRF(addr))) "\tfsubs\t%1\n"
freg: MULD(freg,CVFD(INDIRF(addr))) "\tfmuls\t%1\n"
freg: DIVD(freg,CVFD(INDIRF(addr))) "\tfdivs\t%1\n"
freg: LOADD(memf) "\tfld%0\n"

;;
;; Comparisons between byte/short reg with byte/short memory
;;
stmt: EQI(CVCU(reg),CVCU(INDIRC(addr))) "\tcmpb\t%1,%0\n\tje\t%a\n"
stmt: EQI(CVCI(reg),CVCI(INDIRC(addr))) "\tcmpb\t%1,%0\n\tje\t%a\n"
stmt: NEI(CVCU(reg),CVCU(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjne\t%a\n"
stmt: NEI(CVCI(reg),CVCI(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjne\t%a\n"
stmt: EQI(CVSI(reg),CVSI(INDIRS(addr))) "\tcmpw\t%1,%0\n\tje\t%a\n"
stmt: EQI(CVSU(reg),CVSU(INDIRS(addr))) "\tcmpw\t%1,%0\n\tje\t%a\n"
stmt: NEI(CVSU(reg),CVSU(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjne\t%a\n"
stmt: NEI(CVSI(reg),CVSI(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjne\t%a\n"
stmt: LEI(CVCU(reg),CVCU(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjbe\t%a\n"
stmt: LEI(CVCI(reg),CVCI(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjle\t%a\n"
stmt: LTU(CVCU(reg),CVCU(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjb\t%a\n"
stmt: LTI(CVCI(reg),CVCI(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjl\t%a\n"
stmt: GTI(CVCI(reg),CVCI(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjg\t%a\n"
stmt: GTU(CVCU(reg),CVCU(INDIRC(addr))) "\tcmpb\t%1,%0\n\tja\t%a\n"
stmt: GEI(CVCI(reg),CVCI(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjge\t%a\n"
stmt: GEI(CVCU(reg),CVCU(INDIRC(addr))) "\tcmpb\t%1,%0\n\tjae\t%a\n"
stmt: LEU(CVSU(reg),CVSU(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjbe\t%a\n"
stmt: LEI(CVSI(reg),CVSI(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjle\t%a\n"
stmt: LTI(CVSI(reg),CVSI(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjl\t%a\n"
stmt: LTU(CVSU(reg),CVSU(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjb\t%a\n"
stmt: GTI(CVSI(reg),CVSI(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjg\t%a\n"
stmt: GTU(CVSU(reg),CVSU(INDIRS(addr))) "\tcmpw\t%1,%0\n\tja\t%a\n"
stmt: GEI(CVSI(reg),CVSI(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjge\t%a\n"
stmt: GEU(CVSU(reg),CVSU(INDIRS(addr))) "\tcmpw\t%1,%0\n\tjae\t%a\n"

;;
;; This rule avoids a sequence of instructions like:
;; movsbl  (,%edi),%edx
;; movzbl  %dl,%edx
;; and replaces them for the shorter
;; movzbl  (,%edi),%edx
reg: CVCU(CVUC(CVCI(INDIRC(addr)))) "\tmovzbl\t%0,%c\n"
;;
;; This rule avoids a spurious register assignment when returning the
;; result of a function call.
stmt: RETI(LOADI(reg)) "?\tmovl\t%0,%%eax\n"
;; other RETI rules
stmt: RETI(ADDI(reg,acon)) "\tleal\t%1(%0),%%eax\n"
stmt: RETI(ADDP(reg,acon)) "\tleal\t%1(%0),%%eax\n"
stmt: RETI(zero) "\txor\t%%eax,%%eax\n"
;;
;; 3 adds in one instruction
;;
reg: ADDP(reg,ADDP(reg,acon)) "\tleal\t%2(%0,%1),%c\n"
addr: ADDP(reg,ADDP(reg,acon)) "%2(%0,%1)"
reg: ADDP(ADDP(reg,acon),reg) "\tleal\t%1(%0,%2),%c\n"
addr: ADDP(ADDP(reg,acon),reg) "%1(%0,%2)"
reg: ADDP(ADDP(reg,reg),acon) "\tleal\t%2(%0,%1),%c\n"
addr: ADDP(ADDP(reg,reg),acon) "%2(%0,%1)"
;;
;; The general form of the 'lea' instruction
;;
reg:  ADDP(ADDP(LSHI(reg,icon),reg),acon) "\tleal\t%3(%2,%0,%1),%c\n"
reg:  ADDP(ADDI(LSHI(reg,icon),reg),acon) "\tleal\t%3(%2,%0,%1),%c\n"
addr: ADDP(ADDI(LSHI(reg,icon),reg),acon) "%3(%2,%0,%1)"
addr: ADDP(ADDP(LSHI(reg,icon),reg),acon) "%3(%2,%0,%1)"
addr: ADDP(ADDP(index,reg),baseaddr) "%2(%1,%0)"
addr: ADDP(baseaddr,ADDP(index,reg)) "%0(%2,%1)"
addr: ADDU(ADDU(reg,reg),baseaddr) "%2(%1,%0)"
addr: ADDP(ADDI(LSHI(reg,icon),acon),reg) "%2(%3,%0,%1)"
reg:  ADDP(ADDI(LSHI(reg,icon),acon),reg) "\tleal\t%2(%3,%0,%1),%c\n"
reg:  ADDP(LSHI(reg,icon),reg) "\tleal\t(%2,%0,%1),%c\n"
addr: ADDP(LSHI(reg,icon),reg) "(%2,%0,%1)"
reg:  ADDP(LSHI(reg,icon),ADDP(reg,acon)) "\tleal\t%3(%2,%0,%1),%c\n"
addr: ADDP(LSHI(reg,icon),ADDP(reg,acon)) "%3(%2,%0,%1)"

reg: ADDI(reg,ADDI(reg,acon)) "\tleal\t%2(%0,%1),%c\n"
reg: ADDP(ADDI(reg,acon),reg) "\tleal\t%1(%0,%2),%c\n"
addr: ADDP(ADDI(reg,acon),reg) "%1(%0,%2)"
reg: ADDI(ADDI(reg,acon),reg) "\tleal\t%1(%0,%2),%c\n"
reg: ADDI(ADDI(reg,reg),acon) "\tleal\t%2(%0,%1),%c\n"
;;
;; int 64 support
;;
;; assignment
stmt: ASGNL(INDIRL(addr),freg) "\tfistpq\t%0\n"
stmt: ASGNL(INDIRL(addr),rpair) "\tmovl\t%%eax,%0\n\tleal\t%0,%%eax\n\tmovl\t%%edx,4(%%eax)\n" 3
stmt: ASGNL(addr,freg) "\tfistpq\t%0\n"
stmt: ASGNL(addr,rpair) "\tmovl\t%%eax,%0\n\tleal\t%0,%%eax\n\tmovl\t%%edx,4(%%eax)\n" 3
;;
;; += and +- operations
;;
;;stmt: ASGNL(addr,ADDL(INDIRL(addr),rpair)) "\tleal\t%0,%%ecx\n\taddl\t%%eax,(%%ecx)\n\taddl\t%%edx,4(%%ecx)\n" (LEFT_CHILD(a) != NULL && LEFT_CHILD(a) == LEFT_CHILD(LEFT_CHILD(RIGHT_CHILD(a))))?3:LBURG_MAX
;;stmt: ASGNL(addr,SUBL(INDIRL(addr),rpair)) "\tleal\t%1,%%ecx\n\tsubl\t%%eax,(%%ecx)\n\tsbb\t%%edx,4(%%ecx)\n" (LEFT_CHILD(a) != NULL && LEFT_CHILD(a) == LEFT_CHILD(LEFT_CHILD(RIGHT_CHILD(a))))?3:LBURG_MAX
;;
;; constants
;;
freg: CVIL(con1) "\tfld1\n" 2
freg: CVIL(zero) "\tfldz\n" 2
rpair: CVIL(rc) "\tmovl\t%0,%%eax\n\tcdq\n"
rpair: CVUL(rc) "\tmovl\t%0,%%eax\n\txor\t%%edx,%%edx\n"
;;
;; moving memory to EAX:EDX
;;
rpair:INDIRL(addr) "\tmovl\t%0,%%eax\n\tleal\t%0,%%edx\n\tmovl\t4(%%edx),%%edx\n" 4
;;
;; moving EAX:EDX to st(0)
;;
freg: INDIRL(rpair) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n" 6
;;
;; moving memory to st(0)
;;
freg: INDIRL(addr) "\tfildq\t%0\n"
;;
;; argument pushing
;;
stmt: ARGL(INDIRL(addr)) "\tsubl\t$8,%%esp\n\tfildq\t%0\n\tfistpq\t(%%esp)\n" 3
stmt: ARGL(freg) "\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n" 2
stmt: ARGL(CVIL(rc)) "\tpushl\t$0\n\tpushl\t%0\n" 2
stmt: ARGL(rpair) "\tpushl\t%%edx\n\tpushl\t%%eax\n" 1
;;
;; conversions
;;
freg: CVLD(INDIRL(addr)) "\tfildq\t%0\n"
freg: CVIL(INDIRI(addr)) "\tfildl\t%0\n"
freg: CVIL(rc) "\tpush\t%0\n\tfildl\t(%%esp)\n\taddl\t$4,%%esp\n" 2
freg: CVUL(rc) "\tpush\t$0\n\tpush\t%0\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n"
reg: CVLI(freg) "\tpushl\t%c\n\tfistpl\t(%%esp)\n\tpopl\t%c\n" 2
reg: CVLI(rpair) "\tmovl\t%%eax,%c\n"
reg: CVLI(INDIRL(addr)) "\tmovl\t%0,%c\n"
;;
;; addition
;;
freg: ADDL(INDIRL(addr),CVID(INDIRI(addr))) "\tfildq\t%0\n\tfiaddl\t%1\n"
freg: ADDL(INDIRL(addr),CVIL(con1)) "\tfildq\t%0\n\tfld1\n\tfaddpl\n" 4
freg: ADDL(INDIRL(addr),freg) "\tfildq\t%0\n\tfaddpl\n" 4
freg: ADDL(freg,INDIRL(addr)) "\tfildq\t%1\n\tfaddpl\n" 4
freg: ADDL(freg,CVIL(reg)) "\tpush\t%1\n\tfiaddl\t(%%esp)\n\taddl\t$4,%%esp\n"
rpair: ADDL(addr,rpair) "\tleal\t%0,%%ecx\n\taddl\t(%%ecx),%%eax\n\taddl\t4(%%ecx),%%edx\n" 6
rpair: ADDL(INDIRL(addr),rpair) "\tleal\t%0,%%ecx\n\taddl\t(%%ecx),%%eax\n\tadc\t4(%%ecx),%%edx\n" 6
;;
;; substraction
;;
freg: SUBL(INDIRL(addr),freg) "\tfildq\t%0\n\tfsubpl\n" 1
rpair: SUBL(rpair,INDIRL(addr)) "\tleal\t%1,%%ecx\n\tsubl\t(%%ecx),%%eax\n\tsbb\t4(%%ecx),%%edx\n"
;;
;; multiplication is always done in floating point
freg: MULL(INDIRL(addr),freg) "\tfildq\t%0\n\tfmulpl\n"
freg: MULL(freg,CVIL(INDIRI(addr))) "\tfimull\t%1\n"
;;
;; division
;;
rpair: DIVL(INDIRL(addr),freg) "\t.extern\t__alldiv\n\tsub\t$16,%%esp\n\tfistpq\t8(%%esp)\n\tfildq\t%0\n\tfistpq\t(%%esp)\n\tcall\t__alldiv\n" 7
rpair: DIVL(freg,INDIRL(addr)) "\t.extern\t__alldiv\n\tsub\t$16,%%esp\n\tfistpq\t8(%%esp)\n\tfildq\t%1\n\tfistpq\t(%%esp)\n\tcall\t__alldiv\n" 7
freg: DIVL(INDIRL(addr),freg) "\t.extern\t__alldiv\n\tsub\t$16,%%esp\n\tfistpq\t8(%%esp)\n\tfildq\t%0\n\tfistpq\t(%%esp)\n\tcall\t__alldiv\n\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n" 18
freg: DIVL(freg,INDIRL(addr)) "\t.extern\t__alldiv\n\tsub\t$16,%%esp\n\tfistpq\t(%%esp)\n\tfildq\t%1\n\tfistpq\t8(%%esp)\n\tcall\t__alldiv\n\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n" 18
con32: CNSTI "32" (a->syms[0]->u.c.v.i == 32 ? 0 : LBURG_MAX)
con32: CNSTU "32" (a->syms[0]->u.c.v.u == 32 ? 0 : LBURG_MAX)
;;
;; left shift
;;
rpair: LSHL(rpair,mrc) "\t.extern\t__allshl\n\tmovl\t%1,%%ecx\n\tcall\t__allshl\n" 3
freg: LSHL(freg,mrc) "\t.extern\t__allshl\n\tmovl\t%1,%%ecx\n\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshl\n\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n" 15
freg: LSHL(INDIRL(addr),mrc) "\t.extern\t__allshl\n\tmovl\t%1,%%ecx\n\tsubl\t$8,%%esp\n\tfildq\t%0\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshl\n\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n" 
freg: LSHL(INDIRL(addr),INDIRL(addr)) "\t.extern\t__allshl\n\tmovl\t%1,%%ecx\n\tsubl\t$8,%%esp\n\tfildq\t%0\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshl\n\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n"
;;
;; right shift
;;
rpair: RSHL(rpair,mrc) "\t.extern\t__allshr\n\tmovl\t%1,%%ecx\n\tcall\t__allshr\n" 3
freg: RSHL(freg,mrc) "\t.extern\t__allshr\n\tmovl\t%1,%%ecx\n\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshr\n\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\taddl\t$8,%%esp\n" 15
rpair: RSHL(INDIRL(addr),mrc) "\t.extern\t__allshr\n\tmovl\t%1,%%ecx\n\tfildq\t%0\n\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshr\n"
rpair: RSHL(INDIRL(addr),INDIRL(addr)) "\t.extern\t__allshr\n\tmovl\t%1,%%ecx\n\tfildq\t%0\n\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshr\n" 
rpair: RSHL(INDIRL(addr),con32) "\tleal\t%0,%%eax\n\tmovl\t4(%%eax),%%eax\n\txorl\t%%edx,%%edx\n"
rpair: RSHL(rpair,con32) "\tmovl\t%%edx,%%eax\n\txorl\t%%edx,%%edx\n"
;;
;; logical operations
;;
rpair: BANDL(INDIRL(addr),rpair) "\tleal\t%0,%%ecx\n\tandl\t(%%ecx),%%eax\n\tandl\t4(%%ecx),%%edx\n"
rpair: BORL(INDIRL(addr),rpair) "\tleal\t%0,%%ecx\n\torl\t(%%ecx),%%eax\n\torl\t4(%%ecx),%%edx\n"
rpair: BXORL(INDIRL(addr),rpair) "\tleal\t%0,%%ecx\n\txorl\t(%%ecx),%%eax\n\txorl\t4(%%ecx),%%edx\n"
rpair: BCOML(rpair) "\tnotl\t%%eax\n\tnotl\t%%edx\n"

stmt: ASGNL(addr,LSHL(freg,mrc)) "\t.extern\t__allshl\n\tmovl\t%2,%%ecx\n\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n\tcall\t__allshl\n\tleal\t%0,%%ecx\n\tmovl\t%%eax,(%%ecx)\n\tmovl\t%%edx,4(%%ecx)\n" 8
stmt: ASGNL(addr,LSHL(rpair,mrc)) "\t.extern\t__allshl\n\tmovl\t%2,%%ecx\n\tcall\t__allshl\n\tleal\t%0,%%ecx\n\tmovl\t%%eax,(%%ecx)\n\tmovl\t%%edx,4(%%ecx)\n" 4
;;
;; Modulo operation
;;
freg: MODL(INDIRL(addr),rc) "\tpushl\t%1\n\tfildl\t(%%esp)\n\taddl\t$4,%%esp\n\tfildq\t%0\n\tfprem\n\tfxch\t%%st(1)\n\tfstp\t%%st(0)\n"
freg: MODL(INDIRL(addr),freg) "\tfildq\t%0\n\tfprem\n\tfxch\t%%st(1)\n\tfstp\t%%st(0)\n"
freg: NEGL(freg) "\tfchs\n"
;;
;; comparisons
;;
stmt: LTL(INDIRL(addr),freg) "\tfildq\t%0\n\tfcompp\n\tfstsw\t%%ax\n\tsahf\n\tjb\t%a\n" 10
stmt: LTL(rpair,freg) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\tfcompp\n\tfstsw\t%%ax\n\taddl\t$8,%%esp\n\tsahf\n\tjb\t%a\n"
stmt: GEL(INDIRL(addr),freg) "\tfildq\t%0\n\tfcompp\n\tfstsw\t%%ax\n\tsahf\n\tja\t%a\n"
stmt: GEL(rpair,freg) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\tfcompp\n\tfstsw\t%%ax\n\taddl\t$8,%%esp\n\tsahf\n\tja\t%a\n"
stmt: EQLO(INDIRL(addr),freg) "\tfildq\t%0\n\t\tfcompp\n\tfstsw\t%%ax\n\tandb\t$68,%%ah\n\tcmpb\t$64,%%ah\n\tje\t%a\n"
stmt: EQLO(rpair,freg) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\tfcompp\n\tfstsw\t%%ax\n\tandb\t$68,%%ah\n\taddl\t$8,%%esp\n\tcmpb\t$64,%%ah\n\tje\t%a\n"
stmt: EQLO(freg,INDIRL(addr)) "\tfildq\t%1\n\tfcompp\n\tfstsw\t%%ax\n\tandb\t$68,%%ah\n\tcmpb\t$64,%%ah\n\tje\t%a\n"
stmt: EQLO(freg,freg) "\tfcompp\n\tfstsw\t%%ax\n\tandb\t$68,%%ah\n\tcmpb\t$64,%%ah\n\tje\t%%a\n"
stmt: EQLO(rpair,INDIRL(addr)) "\tleal\t%1,%%ecx\n\tcmpl\t%%eax,(%%ecx)\n\tje\t%a\n\tcmpl\t4(%%ecx),%%edx\n\tje\t%a\n"
stmt: EQLO(INDIRL(addr),rpair) "\tleal\t%0,%%ecx\n\tcmpl\t%%eax,(%%ecx)\n\tje\t%a\n\tcmpl\t4(%%ecx),%%edx\n\tje\t%a\n"
stmt: NEL(INDIRL(addr),freg) "\tfildq\t%0\n\tfcompp\n\tfstsw\t%%ax\n\tandb\t$68,%%ah\n\tje\t%a\n" 8
stmt: NEL(rpair,freg) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\tfcompp\n\tfstsw\t%%ax\n\taddl\t$8,%%esp\n\tandb\t$68,%%ah\n\tje\t%a\n" 10
stmt: NEL(freg,freg) "\tfcompp\n\tfstsw\t%%ax\n\tandb\t$68,%%ah\n\tjne\t%a\n"
stmt: NEL(INDIRL(addr),rpair) "\tcmpl\t%%eax,%0\n\tjne\t%a\n\tleal\t%0,%%eax\n\tcmpl\t%%edx,4(%%eax)\n\tjne\t%a\n"
stmt: GTL(INDIRL(addr),freg) "\tfildq\t%0\n\tfcompp\n\tfstsw %%ax\n\tsahf\n\tja\t%a\n"
stmt: GTL(rpair,freg) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n_tfcompp\n\tfstsw\t%%ax\n\taddl\t$8,%%esp\n\tsahf\n\tja\t%a\n" 10
stmt: LEL(INDIRL(addr),freg) "\tfildq\t%0\n\tfcompp\n\tfstsw %%ax\n\tsahf\n\tjbe\t%a\n"
stmt: LEL(rpair,freg) "\tpushl\t%%edx\n\tpushl\t%%eax\n\tfildq\t(%%esp)\n\tfcompp\n\taddl\t$8,%%esp\n\tfstsw\t%%ax\n\tsahf\n\tjbe\t%a\n" 10
;;
;; To be compatible with microsoft's calling conventions, RETL leaves its
;; results in EAX EDX
stmt: RETL(freg) "\tsubl\t$8,%%esp\n\tfistpq\t(%%esp)\n\tpopl\t%%eax\n\tpopl\t%%edx\n" 6
stmt: RETL(rpair) "# RETL\n"
;;
;;A CALLL should retrieve the EAX EDX result
;;
rpair: CALLL(addrj)  "\tcall\t%0\n\taddl\t$%a,%%esp\n"   hasargs(a)
rpair: CALLL(addrj)  "\tcall\t%0\n" 1
stmt: ASGNL(VREGP,freg) "# write register\n"
stmt: RETI(CVLI(freg)) "\tpushl\t%%eax\n\tfistpl\t(%%esp)\n\tpop\t%%eax\n"
stmt: RETI(rpair) "# RETI(rpair)\n"
freg: CVLD(freg) "# write register\n"
freg: CVDL(freg) "# cvdl\n"
stmt: ARGI(CVCU(CVUC(reg))) "\tpushl\t%0\n"
stmt: NEI(CVCU(CVUC(CVCI(INDIRC(addr)))),con) "\tcmpb\t%1,%0\n\tjne\t%a\n"
;;
reg: JUMPI (con,con) "#escape instruction\n"
;; This rules avoid using up an intermediate register
;;
reg: ADDI(INDIRI(addr),con) "\tmovl\t%0,%c\n\taddl\t%1,%c\n"
reg: ADDU(INDIRI(addr),con) "\tmovl\t%0,%c\n\taddl\t%1,%c\n"
reg: SUBI(INDIRI(addr),con) "\tmovl\t%0,%c\n\tsubl\t%1,%c\n"
reg: SUBU(INDIRI(addr),con) "\tmovl\t%0,%c\n\tsubl\t%1,%c\n"
reg: BANDU(INDIRI(addr),con) "\tmovl\t%0,%c\n\tandl\t%1,%c\n"
reg: BORU(INDIRI(addr),con)  "\tmovl\t%0,%c\n\torl\t%1,%c\n"
reg: RSHI(INDIRI(addr),con) "\tmovl\t%0,%c\n\tsarl\t%1,%c\n"
reg: RSHU(INDIRI(addr),con) "\tmovl\t%0,%c\n\tshrl\t%1,%c\n"

;; I have separated the C files written by people from the C files
;; generated by lburg. I think this simplifies things a bit...
%%
#include "w32incl.c"