📄 ad1819a_initialization_c.asm
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/* ADSP-21060 System Register bit definitions */
#include "def21065l.h"
#include "new65Ldefs.h"
#include <asm_sprt.h>
.GLOBAL _Program_SPORT1_Registers;
.GLOBAL _Program_DMA_Controller;
.GLOBAL _AD1819_Codec_Initialization;
.GLOBAL _tx_buf;
.GLOBAL _rx_buf;
/* AD1819 Codec Register Address Definitions */
#define REGS_RESET 0x0000
#define MASTER_VOLUME 0x0200
#define RESERVED_REG_1 0x0400
#define MASTER_VOLUME_MONO 0x0600
#define RESERVED_REG_2 0x0800
#define PC_BEEP_Volume 0x0A00
#define PHONE_Volume 0x0C00
#define MIC_Volume 0x0E00
#define LINE_IN_Volume 0x1000
#define CD_Volume 0x1200
#define VIDEO_Volume 0x1400
#define AUX_Volume 0x1600
#define PCM_OUT_Volume 0x1800
#define RECORD_SELECT 0x1A00
#define RECORD_GAIN 0x1C00
#define RESERVED_REG_3 0x1E00
#define GENERAL_PURPOSE 0x2000
#define THREE_D_CONTROL_REG 0x2200
#define RESERVED_REG_4 0x2400
#define POWERDOWN_CTRL_STAT 0x2600
#define SERIAL_CONFIGURATION 0x7400
#define MISC_CONTROL_BITS 0x7600
#define SAMPLE_RATE_GENERATE_0 0x7800
#define SAMPLE_RATE_GENERATE_1 0x7A00
#define VENDOR_ID_1 0x7C00
#define VENDOR_ID_2 0x7E00
/* Mask bit selections in Serial Configuration Register for
accessing registers on any of the 3 codecs */
#define MASTER_Reg_Mask 0x1000
#define SLAVE1_Reg_Mask 0x2000
#define SLAVE2_Reg_Mask 0x4000
#define MASTER_SLAVE1 0x3000
#define MASTER_SLAVE2 0x5000
#define MASTER_SLAVE1_SLAVE2 0x7000
/* Macros for setting Bits 15, 14 and 13 in Slot 0 Tag Phase */
#define ENABLE_VFbit_SLOT1_SLOT2 0xE000
#define ENABLE_VFbit_SLOT1 0xC000
/* AD1819 TDM Timeslot Definitions */
#define TAG_PHASE 0
#define COMMAND_ADDRESS_SLOT 1
#define COMMAND_DATA_SLOT 2
#define STATUS_ADDRESS_SLOT 1
#define STATUS_DATA_SLOT 2
#define LEFT 3
#define RIGHT 4
#define AD1819_RESET_CYCLES 60
/* ad1819 RESETb spec = 1.0(uS) min */
/* 60(MIPs) = 16.67 (nS) cycle time, therefore >= 40 cycles */
#define AD1819_WARMUP_CYCLES 60000
/* ad1819 warm-up = 1.0(mS) */
/* 60(MIPs) = 16.67 (nS) cycle time, therefore >= 40000 cycles */
/*---------------------------------------------------------------------------*/
.segment /dm seg_dmda;
.var _rx_buf[5]; /* receive buffer */
/* transmit buffer */
.var _tx_buf[7] = ENABLE_VFbit_SLOT1_SLOT2, /* set valid bits for slot 0, 1, and 2 */
SERIAL_CONFIGURATION, /* serial configuration register address */
0xFF80, /* initially set to 16-bit slot mode for ADI SPORT compatibility*/
0x0000, /* stuff other slots with zeros for now */
0x0000,
0x0000,
0x0000;
/* slots 5 and 6 are dummy slots, to allow enough time in the TX ISR to go */
/* get rx slots 4 & 5 data in same audio frame as the ADC valid tag bits. */
/* This is critical for slower sample rates, where you may not have valid data */
/* every rx audio frame. So you want to make sure there is valid right */
/* channel data in the same rx DMA buffer fill as the detection of an ADC */
/* valid right bit. These extra slots are required ONLY for fs < 48 kHz. */
.var rcv_tcb[8] = 0, 0, 0, 0, 0, 5, 1, 0; /* receive tcb */
.var xmit_tcb[8] = 0, 0, 0, 0, 0, 7, 1, 0; /* transmit tcb */
/* Codec register initializations */
/* Refer to AD1819 Data Sheet for register bit assignments */
#define Select_LINE_INPUTS 0x0404 /* LINE IN - 0X0404, Mic In - 0x0000 */
#define Select_MIC_INPUT 0x0000
#define Line_Level_Volume 0x0000 /* 0 dB for line inputs */
#define Mic_Level_Volume 0x0F0F
#define Sample_Rate 23456
#define Sample_Rate_8kHz 48000
.var Init_Codec_Registers[34] =
MASTER_VOLUME, 0x0000, /* Master Volume set for no attenuation */
MASTER_VOLUME_MONO, 0x8000, /* Master Mono volume is muted */
PC_BEEP_Volume, 0x8000, /* PC volume is muted */
PHONE_Volume, 0x8008, /* Phone Volume is muted */
MIC_Volume, 0x8008, /* MIC Input analog loopback is muted */
LINE_IN_Volume, 0x8808, /* Line Input analog loopback is muted */
CD_Volume, 0x8808, /* CD Volume is muted */
VIDEO_Volume, 0x8808, /* Video Volume is muted */
AUX_Volume, 0x8808, /* AUX Volume is muted */
PCM_OUT_Volume, 0x0808, /* PCM out from DACs is 0 db gain for both channels */
RECORD_SELECT, Select_LINE_INPUTS, /* Record Select on Line Inputs for L/R channels */
RECORD_GAIN, Line_Level_Volume, /* Record Gain set for 0 dB on both L/R channels */
GENERAL_PURPOSE, 0x0000, /* 0x8000, goes through 3D circuitry */
THREE_D_CONTROL_REG, 0x0000, /* no phat stereo */
MISC_CONTROL_BITS, 0x0000, /* use SR0 for both Left and Right ADCs and DACs, repeat sample */
SAMPLE_RATE_GENERATE_0, Sample_Rate_8kHz, /* user selectable sample rate */
SAMPLE_RATE_GENERATE_1, 48000; /* Sample Rate Generator 1 not used in this example */
.var Codec_Init_Results[34] =
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0;
.endseg;
.SEGMENT /pm seg_pmco;
/* ---------------------------------------------------------------------------------------------*/
/* Sport1 Control Register Programming */
/* Multichannel Mode dma w/ chain, erly fs, act hi fs, fall edge, no pack, data=16/big/zero */
/* ---------------------------------------------------------------------------------------------*/
_Program_SPORT1_Registers:
leaf_entry
/* sport1 receive and transmit multichannel word enable registers */
R0 = 0x0000001F; /* enable receive channels 0-4 */
dm(MRCS1) = R0;
R0 = 0x0000007F; /* enable transmit channels 0-6 */
dm(MTCS1) = R0;
/* sport1 transmit and receive multichannel companding enable registers */
R0 = 0x00000000; /* no companding */
dm(MRCCS1) = R0; /* no companding on receive */
dm(MTCCS1) = R0; /* no companding on transmit */
/* sport1 receive frame sync divide register */
R0 = 0x00FF0000; /* SCKfrq(12.288M)/RFSfrq(48.0K)-1 = 0x00FF */
dm(RDIV1) = R0;
/* sport1 transmit control register */
R0 = 0x001C00F0; /* 1 cyc mfd, data depend, slen = 15, sden & schen enabled */
dm(STCTL1) = R0; /* sport 0 transmit control register */
/* sport1 receive control register */
R0 = 0x0F8C40F0; /* 16 chans, int rfs, ext rclk, slen = 15, sden & schen enabled */
dm(SRCTL1) = R0; /* sport 0 receive control register */
leaf_exit;
/*----------------------------------------------------------------------------------*/
/* DMA Controller Programming For SPORT1 */
/*----------------------------------------------------------------------------------*/
_Program_DMA_Controller:
leaf_entry
r1 = 0x0001FFFF; /* cpx register mask */
/* sport1 dma control tx chain pointer register */
r0 = _tx_buf;
dm(xmit_tcb + 7) = r0; /* internal dma address used for chaining*/
r0 = 1;
dm(xmit_tcb + 6) = r0; /* DMA internal memory DMA modifier */
r0 = 7;
dm(xmit_tcb + 5) = r0; /* DMA internal memory buffer count */
r0 = xmit_tcb + 7; /* get DMA chaining internal mem pointer containing tx_buf address */
r0 = r1 AND r0; /* mask the pointer */
r0 = BSET r0 BY 17; /* set the pci bit */
dm(xmit_tcb + 4) = r0; /* write DMA transmit block chain pointer to TCB buffer */
dm(CPT1A) = r0; /* transmit block chain pointer, initiate tx0 DMA transfers */
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/* - Note: Tshift0 & TX0 will be automatically loaded with the first 2 values in the - */
/* - Tx buffer. The Tx buffer pointer ( II3 ) will increment by 2x the modify value - */
/* - ( IM3 ). - */
/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/* sport1 dma control rx chain pointer register */
r0 = _rx_buf;
dm(rcv_tcb + 7) = r0; /* internal dma address used for chaining */
r0 = 1;
dm(rcv_tcb + 6) = r0; /* DMA internal memory DMA modifier */
r0 = 5;
dm(rcv_tcb + 5) = r0; /* DMA internal memory buffer count */
r0 = rcv_tcb + 7;
r0 = r1 AND r0; /* mask the pointer */
r0 = BSET r0 BY 17; /* set the pci bit */
dm(rcv_tcb + 4) = r0; /* write DMA receive block chain pointer to TCB buffer*/
dm(CPR1A) = r0; /* receive block chain pointer, initiate rx0 DMA transfers */
leaf_exit;
/* -------------------------------------------------------------------------------------- */
/* AD1819A Codec Initialization */
/* -------------------------------------------------------------------------------------- */
_AD1819_Codec_Initialization:
leaf_entry
nop;
Enable_SPORT1_MCM_Transfers:
/* enable SPORT1 multichannel operation */
/* Multichannel operation activates 3 cycles after the MCE bit is set */
/* RFS1 activates 4 DSP cycles after this bit is set */
/* R0 = DM(SRCTL1); */ /* load the sport1 control reg */
/* R0 = BSET R0 BY 23;*/ /* set the sport1 multichannel ena bit */
/* DM(SRCTL1) = R0; */ /* prgm the sport1 control reg */
Wait_Codec_Ready: /* wait for codec to be ready */
R0 = DM(_rx_buf + 0); /* get bit 15 status bit from AD1819 tag phase slot 0 */
R1 = 0x8000; /* mask out codec ready bit in tag phase */
R0 = R0 AND R1; /* test the codec ready status flag bit */
IF EQ JUMP Wait_Codec_Ready; /* if flag is lo, continue to wait for a hi */
idle; /* wait for a couple of TDM audio frames to pass */
idle;
Initialize_1819_Registers:
i4 = Init_Codec_Registers; /* pointer to codec initialization commands */
r12 = ENABLE_VFbit_SLOT1_SLOT2; /* enable valid frame bit, and slots 1 and 2 valid data bits */
LCNTR = 17, DO Codec_Init UNTIL LCE;
dm(_tx_buf + TAG_PHASE) = r12; /* set valid slot bits in tag phase for slots 0, 1 , 2 */
r1 = dm(i4, 1); /* fetch next codec register address */
dm(_tx_buf + COMMAND_ADDRESS_SLOT) = r1;/* put fetched codec register address into tx slot 1 */
r1 = dm(i4, 1); /* fetch register data contents */
dm(_tx_buf + COMMAND_DATA_SLOT) = r1; /* put fetched codec register data into tx slot 2 */
Codec_Init: idle; /* wait until TDM frame is transmitted */
/*------------------------------------------------------------------------------------------------------*/
/* Verify integrity of AD1819a indexed control register states to see if communication was successful */
/*------------------------------------------------------------------------------------------------------*/
/* This section of codes is for debugging/verification of AD1819 registers. Theses instructions */
/* initiate codec read requests of registers shown in the Init_Codec_Registers buffer. The results */
/* of the read requests are placed in an output buffer called Codec_Init_Results, in which even */
/* DSP memory addresses contain the AD1819A register address, and the DSP's odd address in the buffer */
/* contains the register data for the AD1819A address. The AD1819A registers can then be verified with */
/* a JTAG emulator or debug monitor program. This section of code can be removed after debug. */
/*------------------------------------------------------------------------------------------------------*/
verify_reg_writes:
i4 = Init_Codec_Registers;
m4 = 2;
i13 = Codec_Init_Results;
r12 = ENABLE_VFbit_SLOT1; /* enable valid frame bit, and slots 1 data bits */
LCNTR = 17, Do ad1819_register_status UNTIL LCE;
dm(_tx_buf + TAG_PHASE) = r12; /* set valid slot bits in tag phase for slots 0, 1 , 2 */
r1 = dm(i4,2); /* get indexed register address that is to be inspected */
r2 = 0x8000; /* set bit #15 for read request in command address word */
r1 = r1 OR r2; /* OR read request with the indirect register value */
dm(_tx_buf + COMMAND_ADDRESS_SLOT) = r1; /* send value out of command address timeslot */
idle; /* wait for 2 audio frame to go by, latency in getting data */
idle;
r0 = dm(_rx_buf + STATUS_ADDRESS_SLOT);
pm(i13,1) = r0;
r0 = dm(_rx_buf + STATUS_DATA_SLOT); /* fetch value of requested indexed register data */
pm(i13,1) = r0; /* store to results buffer */
ad1819_register_status: nop;
/* ---------------------------------------------------------------------------------------------------- */
/* For variable sample rate support, you must powerdown and powerback up the ADCs and DACs */
/* so that the incoming ADC data and DAC requests occur in left/right pairs */
/* ---------------------------------------------------------------------------------------------------- */
PowerDown_DACs_ADCs:
idle;
r12 = ENABLE_VFbit_SLOT1_SLOT2; /* enable valid frame bit, and slots 1 and 2 valid data bits */
dm(_tx_buf + TAG_PHASE) = r12; /* set valid slot bits in tag phase for slots 0, 1 , 2 */
r0=POWERDOWN_CTRL_STAT;
dm(_tx_buf + COMMAND_ADDRESS_SLOT) = r0;
r0=0x0300; /* power down all DACs/ADCs */
dm(_tx_buf + COMMAND_DATA_SLOT) = r0;
idle;
idle;
LCNTR = AD1819_RESET_CYCLES-2, DO reset_loop UNTIL LCE;
reset_loop: NOP; /* wait for the min RESETb lo spec time */
idle;
r12 = ENABLE_VFbit_SLOT1_SLOT2; /* enable valid frame bit, and slots 1 and 2 valid data bits */
dm(_tx_buf + TAG_PHASE) = r12; /* set valid slot bits in tag phase for slots 0, 1 , 2 */
r0=POWERDOWN_CTRL_STAT; /* address to write to */
dm(_tx_buf + COMMAND_ADDRESS_SLOT) = r0;
r0=0; /* power up all DACs/ADCs */
dm(_tx_buf + COMMAND_DATA_SLOT) = r0;
idle;
idle;
LCNTR = AD1819_WARMUP_CYCLES-2, DO warmup_loop2 UNTIL LCE;
warmup_loop2: NOP; /* wait for AD1819 warm-up */
leaf_exit;
/* ------------------------------------------------------------------------------------------- */
.endseg;
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