clear_spt1_regs.asm

ADI公司的ADSP21065L的专业数字音频处理器的源代码

/* /////////////////////////////////////////////////////////////////////////////////////////
/                                                                                          /
/   ROUTINE TO CLEAR AND RESET ALL SPORT1 REGISTERS                                        /
/                                                                                          /
/   This routine may be required for certaing AD1819A demos when using the 21065L EZ-LAB   /
/   RS232 Debug Monitor program.  The 21065L EZ-LAB boot EPROM Monitor kernel on power-up  /
/   executes a routine that programs the SPORT1 Control and DMA registers to               /
/   communicate with the AD1819A for the example supplied EZ-LAB demo programs.            /
/                                                                                          /
/   When invoking the 65L VDSP RS232 Debugger, SPORT1 DMA is already active in             /
/   multichannel mode with DMA chaining.  If we wish to leave the SPORT TDM and DMA        /
/   channel configuration the same (i.e. 5 active channels and 5-word DMA buffers),        /
/   we are usually still able to reprogram the DMA controller to point to our own          /
/   own codec buffers with no side effects.  However, if we need to change any SPORT       /
/   control parameters such as the number of active TDM channels and DMA buffer sizes,     /
/   then the active EPROM Monitor SPORT TDM configuration on powerup of the EZ-LAB board   /
/   will affect the re-programming of the SPORT within a downloaded DSP executable.        /
/                                                                                          /
/   Since the monitor program has already activated the SPORT1 registers after a board     /
/   reset, the side effect that occurs (when re-writing over the SPORT1 control            /
/   registers) is that MCM DMA data transfers are mistakingly restarted                    /
/   without the full programming of all the SPORT parameters.  Also, the TX and            /
/   RX buffers may be partially full or full, and can affect the DMA controller's          /
/   ability to correctly DMA in/out SPORT data to/from internal memory.  What results      /
/   is a failed link between the AD1819a and SPORT1 in user-modifed code, because          /
/   transmitted and recieved data is sent or received in different timeslots and misalign  /
/   in the SPORT DMA buffers.                                                              /
/                                                                                          /
/   This routine simply clears all SPORT1 ctrl and DMA registers back to their             /
/   default states so that we can reconfigure it for our AD1819a application.              /
/                                                                                          /
/   When using the SHARC JTAG ICE, this routine is not required and can be removed. For    /
/   operation of the EZ-ICE with the 21065L EZ-LAB, we recommend removing the Monitor      /
/   EPROM from the board to prevent the EPROM Monitor's UART/AD1819 initialization. The    /
/   UART chip, once initialized, can hold ACK low to prevent the ICE software from         /
/   starting, because the JTAG port cannot gain access to DSP resources with ACK low       /
/                                                                                          /
/   John Tomarakos                                                                         /
/   ADI DSP Applications                                                                   /
/   Rev 1.1                                                                                /
/   9/24/99                                                                                /
/                                                                                          /
///////////////////////////////////////////////////////////////////////////////////////// */

/* ADSP-21060 System Register bit definitions */
#include 	"def21065l.h"
#include 	"new65Ldefs.h"
#include 	<asm_sprt.h>


.GLOBAL		_Clear_All_SPT1_Regs;

.SEGMENT /pm 	seg_pmco;

_Clear_All_SPT1_Regs:

	leaf_entry

	IRPTL = 0x00000000;		/* clear pending interrupts */
	bit clr imask SPT1I; 

	R0 = 0x00000000;			
	dm(SRCTL1) = R0;		/* sport1 receive control register */				
	dm(RDIV1) = R0;			/* sport1 receive frame sync divide register */		
	dm(STCTL1) = R0;		/* sport 0 transmit control register */
	dm(MRCS1) = R0;			/* sport1 receive multichannel word enable register */
	dm(MTCS1) = R0;			/* sport1 transmit multichannel word enable register */
	dm(MRCCS1) = R0;		/* sport1 receive multichannel companding enable register */
	dm(MTCCS1) = R0;		/* sport1 transmit multichannel companding enable register */

	/* reset SPORT1 DMA parameters back to the Reset Default State */
	R1 = 0x1FFFF; 	dm(IIR1A) = R1; 
	R1 = 0x0001; 	dm(IMR1A) = R1;	
	R1 = 0xFFFF;	dm(CR1A)  = R1;	
	R1 = 0x1FFFF;	dm(CPR1A) = R1; 		
	R1 = 0x1FFFF;	dm(GPR1A) = R1;	
	R1 = 0x1FFFF;	dm(IIT1A) = R1;
	R1 = 0x0001;	dm(IMT1A) = R1;
	R1 = 0xFFFF;	dm(CT1A)  = R1;
	R1 = 0x1FFFF;	dm(CPT1A) = R1;
	R1 = 0x1FFFF;	dm(GPT1A) = R1;
	
   	leaf_exit;

.ENDSEG;