logdemo.m

本书是电子通信类的本科、研究生辅助教材

		'position',[50,95,70,115])

add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/in_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/in_1']],...
		'Port','2',...
		'position',[15,75,35,95])

add_block('built-in/Transport Delay',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Transport Delay1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Transport Delay1']],...
		'Initial Input','1',...
		'position',[65,25,115,55])

add_block('built-in/Combinatorial Logic',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/NOT1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/NOT1']],...
		'Truth Table','[1;0]',...
		'Mask Display','NOT',...
		'Mask Type','NOT',...
		'Mask Dialogue','NOT Gate',...
		'Mask Help','Negates the input.')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/NOT1']],...
		'position',[135,28,170,52])


%     Subsystem  ['Modulo-4',13,'Counter/JK flip-flop2/AND'].

new_system([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],'Location',[59,237,323,377])

add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/in_2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/in_2']],...
		'Port','2',...
		'position',[15,70,35,90])

add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/in_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/in_1']],...
		'position',[15,55,35,75])

add_block('built-in/Mux',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/Mux']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/Mux']],...
		'inputs','2',...
		'position',[65,55,95,90])

add_block('built-in/Combinatorial Logic',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/AND']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/AND']],...
		'Truth Table','[0;0;0;1]',...
		'position',[130,55,185,95])

add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/out_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND/out_1']],...
		'position',[215,65,235,85])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],[190,75;210,75])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],[40,80;60,80])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],[40,65;60,65])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],[100,75;125,75])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],...
		'Mask Display','AND',...
		'Mask Type','AND',...
		'Mask Dialogue','AND Gate',...
		'Mask Help','Calculates the logical AND of the two inputs.')


%     Finished composite block ['Modulo-4',13,'Counter/JK flip-flop2/AND'].

set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/AND']],...
		'position',[200,34,235,61])

add_block('built-in/Mux',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Mux']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Mux']],...
		'position',[300,87,330,133])

add_block('built-in/Combinatorial Logic',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Logic']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Logic']],...
		'Truth Table','[0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0;1 0;0 1]',...
		'position',[360,90,415,130])

add_block('built-in/Demux',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Demux']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Demux']],...
		'outputs','2',...
		'position',[435,90,475,125])

add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/out_2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/out_2']],...
		'Port','2',...
		'position',[520,105,540,125])

add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/out_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/out_1']],...
		'position',[550,90,570,110])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[285,185;250,185;250,125;295,125])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[395,185;335,185])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[240,50;255,50;255,95;295,95])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[40,85;175,85;175,55;195,55])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[175,40;195,40])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[120,40;130,40])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[40,85;40,40;60,40])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[75,105;295,105])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[100,115;295,115])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[480,115;515,115])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[480,100;545,100])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[420,110;430,110])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[335,110;355,110])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],[480,100;500,100;500,185;450,185])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],...
		'Mask Display','J    1\n\n>        \n\nK    0',...
		'Mask Type','JK flip-flop',...
		'Mask Dialogue','JK flip-flop|Initial State for Output "1":')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],...
		'Mask Help','When the clock signal is high, if the uncomp- lemented output is currently zero and J becomes one, the output will change to one.  K has no effect on the output in this case.  If the current value of the uncomplemented output is one and K becomes one, the output will change to zero.  J will have no effect on the output in this case.  The system clock period is used to set the state feedback delay of the flip-flop.')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],...
		'Mask Entries','0\/')


%     Finished composite block ['Modulo-4',13,'Counter/JK flip-flop2'].

set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],...
		'Drop Shadow',4,...
		'position',[325,112,370,188])
add_line([sys,'/',['Modulo-4',13,'Counter']],[85,120;150,120])
add_line([sys,'/',['Modulo-4',13,'Counter']],[130,120;130,170;150,170])
add_line([sys,'/',['Modulo-4',13,'Counter']],[85,210;100,210;100,145;150,145])
add_line([sys,'/',['Modulo-4',13,'Counter']],[100,210;290,210;290,150;320,150])
add_line([sys,'/',['Modulo-4',13,'Counter']],[205,125;320,125])
add_line([sys,'/',['Modulo-4',13,'Counter']],[300,125;300,175;320,175])
add_line([sys,'/',['Modulo-4',13,'Counter']],[375,130;415,130])
add_line([sys,'/',['Modulo-4',13,'Counter']],[225,125;225,155;245,155])


%     Finished composite block ['Modulo-4',13,'Counter'].

set_param([sys,'/',['Modulo-4',13,'Counter']],...
		'ForeGround',2,...
		'Drop Shadow',4,...
		'position',[150,120,180,175])

add_block('built-in/Note',[sys,'/','ouput pulse'])
set_param([sys,'/','ouput pulse'],...
		'position',[640,210,645,215])

add_block('built-in/Note',[sys,'/','clock'])
set_param([sys,'/','clock'],...
		'position',[620,270,625,275])

add_block('built-in/Note',[sys,'/','counter MSB'])
set_param([sys,'/','counter MSB'],...
		'position',[645,230,650,235])

add_block('built-in/Note',[sys,'/','counter LSB'])
set_param([sys,'/','counter LSB'],...
		'position',[640,250,645,255])


%     Subsystem  'Display'.

new_system([sys,'/','Display'])
set_param([sys,'/','Display'],'Location',[426,219,899,692])

add_block('built-in/Inport',[sys,'/','Display/in_3'])
set_param([sys,'/','Display/in_3'],...
		'Port','3',...
		'position',[25,230,45,250])

add_block('built-in/Inport',[sys,'/','Display/in_2'])
set_param([sys,'/','Display/in_2'],...
		'Port','2',...
		'position',[25,205,45,225])

add_block('built-in/Inport',[sys,'/','Display/in_1'])
set_param([sys,'/','Display/in_1'],...
		'position',[25,180,45,200])

add_block('built-in/Inport',[sys,'/','Display/in_4'])
set_param([sys,'/','Display/in_4'],...
		'Port','4',...
		'position',[25,255,45,275])

add_block('built-in/Mux',[sys,'/','Display/Mux'])
set_param([sys,'/','Display/Mux'],...
		'position',[160,173,190,282])

add_block('built-in/Scope',[sys,'/','Display/Scope'])
set_param([sys,'/','Display/Scope'],...
		'Vgain','2.700000',...
		'Hgain','10.000000',...
		'Vmax','5.400000',...
		'Hmax','20.000000',...
		'Window',[538,277,922,443])
open_system([sys,'/','Display/Scope'])
set_param([sys,'/','Display/Scope'],...
		'position',[315,212,335,238])

add_block('built-in/Sum',[sys,'/','Display/Sum'])
set_param([sys,'/','Display/Sum'],...
		'position',[240,215,260,235])

add_block('built-in/Constant',[sys,'/','Display/Constant'])
set_param([sys,'/','Display/Constant'],...
		'Value','[1.3 0.1 -1.2 -2.4]',...
		'position',[80,108,190,132])
add_line([sys,'/','Display'],[195,120;215,120;215,220;235,220])
add_line([sys,'/','Display'],[265,225;310,225])
add_line([sys,'/','Display'],[195,230;235,230])
add_line([sys,'/','Display'],[50,215;155,215])
add_line([sys,'/','Display'],[50,190;155,190])
add_line([sys,'/','Display'],[50,240;155,240])
add_line([sys,'/','Display'],[50,265;155,265])


%     Finished composite block 'Display'.

set_param([sys,'/','Display'],...
		'Drop Shadow',4,...
		'position',[555,206,595,294])


%     Subsystem  'Clock'.

new_system([sys,'/','Clock'])
set_param([sys,'/','Clock'],'Location',[471,305,910,612])

add_block('built-in/Constant',[sys,'/','Clock/Constant'])
set_param([sys,'/','Clock/Constant'],...
		'position',[25,25,45,45])

add_block('built-in/Outport',[sys,'/','Clock/out_1'])
set_param([sys,'/','Clock/out_1'],...
		'position',[240,30,260,50])

add_block('built-in/Unit Delay',[sys,'/','Clock/Unit Delay'])
set_param([sys,'/','Clock/Unit Delay'],...
		'orientation',2,...
		'Sample time','duration',...
		'position',[125,80,175,100])

add_block('built-in/Sum',[sys,'/','Clock/Sum'])
set_param([sys,'/','Clock/Sum'],...
		'inputs','+-',...
		'position',[115,30,135,50])
add_line([sys,'/','Clock'],[140,40;235,40])
add_line([sys,'/','Clock'],[120,90;85,90;85,45;110,45])
add_line([sys,'/','Clock'],[140,40;210,40;210,90;180,90])
add_line([sys,'/','Clock'],[50,35;110,35])
set_param([sys,'/','Clock'],...
		'Mask Display','plot(0,0,100,100,[90,75,75,60,60,35,35,20,20,10],[20,20,80,80,19,20,80,80,20,20])',...
		'Mask Type','Digital clock')
set_param([sys,'/','Clock'],...
		'Mask Dialogue','Digital clock.\nOutput is set to 1 for the first half of the period.|Period:',...
		'Mask Translate','duration = @1/2;',...
		'Mask Help','Digital clock for logic systems.')
set_param([sys,'/','Clock'],...
		'Mask Entries','1\/')


%     Finished composite block 'Clock'.

set_param([sys,'/','Clock'],...
		'ForeGround',6,...
		'position',[60,266,100,294])

add_block('built-in/Logical Operator',[sys,'/',['Logical',13,'operator']])
set_param([sys,'/',['Logical',13,'operator']],...
		'hide name',0,...
		'Operator','AND',...
		'position',[475,157,510,188])

add_block('built-in/Logical Operator',[sys,'/',['Logical',13,'operator3']])
set_param([sys,'/',['Logical',13,'operator3']],...
		'hide name',0,...
		'Operator','AND',...
		'position',[330,121,360,174])

add_block('built-in/Logical Operator',[sys,'/',['Logical',13,'operator1']])
set_param([sys,'/',['Logical',13,'operator1']],...
		'hide name',0,...
		'Operator','NOT',...
		'Number of Input Ports','1',...
		'position',[330,180,360,200])

add_block('built-in/Logical Operator',[sys,'/',['Logical',13,'operator2']])
set_param([sys,'/',['Logical',13,'operator2']],...
		'hide name',0,...
		'Operator','NOT',...
		'Number of Input Ports','1',...
		'position',[270,150,300,170])
add_line(sys,[185,135;325,135])
add_line(sys,[365,150;375,150;375,165;390,165])
add_line(sys,[305,160;325,160])
add_line(sys,[185,160;265,160])
add_line(sys,[365,190;390,190])
add_line(sys,[435,165;470,165])
add_line(sys,[105,280;550,280])
add_line(sys,[305,280;305,190;325,190])
add_line(sys,[120,280;120,150;145,150])
add_line(sys,[210,160;210,260;550,260])
add_line(sys,[230,135;230,240;550,240])
add_line(sys,[515,175;535,175;535,220;550,220])
add_line(sys,[450,280;450,180;470,180])

% Return any arguments.
if (nargin | nargout)
	% Must use feval here to access system in memory
	if (nargin > 3)
		if (flag == 0)
			eval(['[ret,x0,str]=',sys,'(t,x,u,flag);'])
		else
			eval(['ret =', sys,'(t,x,u,flag);'])
		end
	else
		[ret,x0,str] = feval(sys);
	end
end