📄 logdemo.m
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function [ret,x0,str]=logdemo(t,x,u,flag);
%LOGDEMO is the M-file description of the SIMULINK system named LOGDEMO.
% The block-diagram can be displayed by typing: LOGDEMO.
%
% SYS=LOGDEMO(T,X,U,FLAG) returns depending on FLAG certain
% system values given time point, T, current state vector, X,
% and input vector, U.
% FLAG is used to indicate the type of output to be returned in SYS.
%
% Setting FLAG=1 causes LOGDEMO to return state derivatives, FLAG=2
% discrete states, FLAG=3 system outputs and FLAG=4 next sample
% time. For more information and other options see SFUNC.
%
% Calling LOGDEMO with a FLAG of zero:
% [SIZES]=LOGDEMO([],[],[],0), returns a vector, SIZES, which
% contains the sizes of the state vector and other parameters.
% SIZES(1) number of states
% SIZES(2) number of discrete states
% SIZES(3) number of outputs
% SIZES(4) number of inputs.
% For the definition of other parameters in SIZES, see SFUNC.
% See also, TRIM, LINMOD, LINSIM, EULER, RK23, RK45, ADAMS, GEAR.
% Note: This M-file is only used for saving graphical information;
% after the model is loaded into memory an internal model
% representation is used.
% the system will take on the name of this mfile:
sys = mfilename;
new_system(sys)
simver(1.3)
if (0 == (nargin + nargout))
set_param(sys,'Location',[335,535,1042,882])
open_system(sys)
end;
set_param(sys,'algorithm', 'RK-45')
set_param(sys,'Start time', '0.0')
set_param(sys,'Stop time', '9.9')
set_param(sys,'Min step size', '0.005')
set_param(sys,'Max step size', '.01')
set_param(sys,'Relative error','1e-3')
set_param(sys,'Return vars', '')
add_block('built-in/Note',[sys,'/','Digital Pulse Generator'])
set_param([sys,'/','Digital Pulse Generator'],...
'position',[390,15,395,20])
add_block('built-in/Note',[sys,'/',['This system takes the output of the Modulo-4 counter and ',13,'generates a 1//2 clock cycle width pulse on every fourth clock pulse.',13,'Effectively, it produces a pulse whenever the value of the counter ',13,'output is one (01).']])
set_param([sys,'/',['This system takes the output of the Modulo-4 counter and ',13,'generates a 1//2 clock cycle width pulse on every fourth clock pulse.',13,'Effectively, it produces a pulse whenever the value of the counter ',13,'output is one (01).']],...
'position',[390,46,395,51])
% Subsystem 'D flip-flop'.
new_system([sys,'/','D flip-flop'])
set_param([sys,'/','D flip-flop'],'Location',[105,262,408,422])
add_block('built-in/Demux',[sys,'/','D flip-flop/Demux'])
set_param([sys,'/','D flip-flop/Demux'],...
'outputs','2',...
'position',[210,50,250,85])
add_block('built-in/Mux',[sys,'/','D flip-flop/Mux1'])
set_param([sys,'/','D flip-flop/Mux1'],...
'inputs','3',...
'position',[80,47,110,93])
add_block('built-in/Combinatorial Logic',[sys,'/','D flip-flop/Logic'])
set_param([sys,'/','D flip-flop/Logic'],...
'Truth Table','[0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0]',...
'position',[130,50,185,90])
add_block('built-in/Transport Delay',[sys,'/','D flip-flop/Transport Delay'])
set_param([sys,'/','D flip-flop/Transport Delay'],...
'orientation',2,...
'position',[140,115,185,145])
add_block('built-in/Inport',[sys,'/','D flip-flop/in_1'])
set_param([sys,'/','D flip-flop/in_1'],...
'Port','2',...
'position',[30,45,50,65])
add_block('built-in/Outport',[sys,'/','D flip-flop/out_1'])
set_param([sys,'/','D flip-flop/out_1'],...
'position',[290,50,310,70])
add_block('built-in/Outport',[sys,'/','D flip-flop/out_2'])
set_param([sys,'/','D flip-flop/out_2'],...
'Port','2',...
'position',[280,65,300,85])
add_block('built-in/Inport',[sys,'/','D flip-flop/in_2'])
set_param([sys,'/','D flip-flop/in_2'],...
'position',[30,60,50,80])
add_line([sys,'/','D flip-flop'],[115,70;125,70])
add_line([sys,'/','D flip-flop'],[190,70;205,70])
add_line([sys,'/','D flip-flop'],[255,60;275,60;275,130;190,130])
add_line([sys,'/','D flip-flop'],[135,130;55,130;55,85;75,85])
add_line([sys,'/','D flip-flop'],[55,55;75,55])
add_line([sys,'/','D flip-flop'],[55,70;75,70])
add_line([sys,'/','D flip-flop'],[255,60;285,60])
add_line([sys,'/','D flip-flop'],[255,75;275,75])
set_param([sys,'/','D flip-flop'],...
'Mask Display','D 1\n\n> 0',...
'Mask Type','D flip-flop',...
'Mask Dialogue','D flip-flop')
set_param([sys,'/','D flip-flop'],...
'Mask Help','While the clock signal is high, the ouput will be the same as the input signal. The flip-flop then latches to the value of the input at the trailing edge of the clock pulse for the remainder to the clock cycle.')
% Finished composite block 'D flip-flop'.
set_param([sys,'/','D flip-flop'],...
'Drop Shadow',4,...
'position',[395,152,430,203])
% Subsystem ['Modulo-4',13,'Counter'].
new_system([sys,'/',['Modulo-4',13,'Counter']])
set_param([sys,'/',['Modulo-4',13,'Counter']],'Location',[474,84,1019,428])
add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/Low-Order',13,'Bit']])
set_param([sys,'/',['Modulo-4',13,'Counter/Low-Order',13,'Bit']],...
'Port','2',...
'position',[250,145,270,165])
add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/High-Order',13,'Bit']])
set_param([sys,'/',['Modulo-4',13,'Counter/High-Order',13,'Bit']],...
'position',[420,120,440,140])
add_block('built-in/Constant',[sys,'/',['Modulo-4',13,'Counter/Constant']])
set_param([sys,'/',['Modulo-4',13,'Counter/Constant']],...
'position',[60,110,80,130])
add_block('built-in/Note',[sys,'/',['Modulo-4',13,'Counter/This system ouputs the binary sequence',13,'11 00 01 10']])
set_param([sys,'/',['Modulo-4',13,'Counter/This system ouputs the binary sequence',13,'11 00 01 10']],...
'position',[265,35,270,40])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/Clock']])
set_param([sys,'/',['Modulo-4',13,'Counter/Clock']],...
'ForeGround',6,...
'position',[60,200,80,220])
% Subsystem ['Modulo-4',13,'Counter/JK flip-flop1'].
new_system([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],'Location',[337,161,940,393])
add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/out_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/out_1']],...
'position',[550,90,570,110])
add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/out_2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/out_2']],...
'Port','2',...
'position',[520,105,540,125])
add_block('built-in/Demux',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Demux']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Demux']],...
'outputs','2',...
'position',[435,90,475,125])
add_block('built-in/Combinatorial Logic',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Logic']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Logic']],...
'Truth Table','[0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0;1 0;0 1]',...
'position',[360,90,415,130])
add_block('built-in/Mux',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Mux']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Mux']],...
'position',[300,87,330,133])
% Subsystem ['Modulo-4',13,'Counter/JK flip-flop1/AND'].
new_system([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],'Location',[59,237,323,377])
add_block('built-in/Outport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/out_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/out_1']],...
'position',[215,65,235,85])
add_block('built-in/Combinatorial Logic',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/AND']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/AND']],...
'Truth Table','[0;0;0;1]',...
'position',[130,55,185,95])
add_block('built-in/Mux',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/Mux']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/Mux']],...
'inputs','2',...
'position',[65,55,95,90])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/in_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/in_1']],...
'position',[15,55,35,75])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/in_2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND/in_2']],...
'Port','2',...
'position',[15,70,35,90])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],[100,75;125,75])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],[40,65;60,65])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],[40,80;60,80])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],[190,75;210,75])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],...
'Mask Display','AND',...
'Mask Type','AND',...
'Mask Dialogue','AND Gate',...
'Mask Help','Calculates the logical AND of the two inputs.')
% Finished composite block ['Modulo-4',13,'Counter/JK flip-flop1/AND'].
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/AND']],...
'position',[200,34,235,61])
add_block('built-in/Combinatorial Logic',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/NOT1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/NOT1']],...
'Truth Table','[1;0]',...
'Mask Display','NOT',...
'Mask Type','NOT',...
'Mask Dialogue','NOT Gate',...
'Mask Help','Negates the input.')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/NOT1']],...
'position',[135,28,170,52])
add_block('built-in/Transport Delay',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Transport Delay1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Transport Delay1']],...
'Initial Input','1',...
'position',[65,25,115,55])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/in_1']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/in_1']],...
'Port','2',...
'position',[15,75,35,95])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/in_2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/in_2']],...
'position',[50,95,70,115])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/in_3']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/in_3']],...
'Port','3',...
'position',[75,105,95,125])
add_block('built-in/Fcn',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Fcn']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Fcn']],...
'orientation',2,...
'Expr','u[1]>.2',...
'position',[290,175,330,195])
add_block('built-in/Transport Delay',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Transport Delay']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1/Transport Delay']],...
'orientation',2,...
'Initial Input','ini',...
'position',[400,170,445,200])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[480,100;500,100;500,185;450,185])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[335,110;355,110])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[420,110;430,110])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[480,100;545,100])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[480,115;515,115])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[100,115;295,115])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[75,105;295,105])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[40,85;40,40;60,40])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[120,40;130,40])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[175,40;195,40])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[40,85;175,85;175,55;195,55])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[240,50;255,50;255,95;295,95])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[395,185;335,185])
add_line([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],[285,185;250,185;250,125;295,125])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],...
'Mask Display','J 1\n\n> \n\nK 0',...
'Mask Type','JK flip-flop',...
'Mask Dialogue','JK flip-flop|Initial State for Output "1":')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],...
'Mask Translate','ini=(@1~=0);')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],...
'Mask Help','When the clock signal is high, if the uncomp- lemented output is currently zero and J becomes one, the output will change to one. K has no effect on the output in this case. If the current value of the uncomplemented output is one and K becomes one, the output will change to zero. J will have no effect on the output in this case. The system clock period is used to set the state feedback delay of the flip-flop.')
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],...
'Mask Entries','0\/')
% Finished composite block ['Modulo-4',13,'Counter/JK flip-flop1'].
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop1']],...
'Drop Shadow',4,...
'position',[155,107,200,183])
% Subsystem ['Modulo-4',13,'Counter/JK flip-flop2'].
new_system([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2']],'Location',[337,161,940,393])
add_block('built-in/Transport Delay',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Transport Delay']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Transport Delay']],...
'orientation',2,...
'Initial Input','ini',...
'position',[400,170,445,200])
add_block('built-in/Fcn',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Fcn']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/Fcn']],...
'orientation',2,...
'Expr','u[1]>.2',...
'position',[290,175,330,195])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/in_3']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/in_3']],...
'Port','3',...
'position',[75,105,95,125])
add_block('built-in/Inport',[sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/in_2']])
set_param([sys,'/',['Modulo-4',13,'Counter/JK flip-flop2/in_2']],...
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