leda.map.rpt

VHDL流水灯程序

; Timing-Driven Synthesis                                      ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                ; Off                ;
; Synchronization Register Chain Length                        ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation ; Normal compilation ;
; HDL message level                                            ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                ; 100                ;
; Clock MUX Protection                                         ; On                 ; On                 ;
; Auto Gated Clock Conversion                                  ; Off                ; Off                ;
; Block Design Naming                                          ; Auto               ; Auto               ;
; SDC constraint protection                                    ; Off                ; Off                ;
; Synthesis Effort                                             ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                 ; On                 ;
; Analysis & Synthesis Message Level                           ; Medium             ; Medium             ;
+--------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                              ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                 ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; LEDA.vhd                         ; yes             ; User VHDL File  ; G:/做视频教材要用的/VHDL/LED流水灯A/LEDA.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 75    ;
;                                             ;       ;
; Total combinational functions               ; 75    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 28    ;
;     -- 3 input functions                    ; 12    ;
;     -- <=2 input functions                  ; 35    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 49    ;
;     -- arithmetic mode                      ; 26    ;
;                                             ;       ;
; Total registers                             ; 39    ;
;     -- Dedicated logic registers            ; 39    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 9     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 25    ;
; Total fan-out                               ; 337   ;
; Average fan-out                             ; 2.74  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |LEDA                      ; 75 (75)           ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 9    ; 0            ; |LEDA               ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 39    ;
; Number of registers using Synchronous Clear  ; 24    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 12    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |LEDA|\P1:count[23]        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Wed Apr 14 21:14:00 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LEDA -c LEDA
Info: Found 2 design units, including 1 entities, in source file LEDA.vhd
    Info: Found design unit 1: LEDA-light
    Info: Found entity 1: LEDA
Info: Elaborating entity "LEDA" for the top level hierarchy
Info: Implemented 84 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 8 output pins
    Info: Implemented 75 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 194 megabytes
    Info: Processing ended: Wed Apr 14 21:14:02 2010
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02